4 interrupt request level register (irlr), Interrupt request level register (irlr) -10 – Freescale Semiconductor MCF5480 User Manual
Page 362
MCF548x Reference Manual, Rev. 3
13-10
Freescale Semiconductor
13.2.1.4
Interrupt Request Level Register (IRLR)
This 7-bit register is updated each machine cycle and represents the current interrupt requests for each
interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc.
13.2.1.5
Interrupt Acknowledge Level and Priority Register (IACKLPR)
Each time an IACK is performed, the interrupt controller responds with the vector number of the highest
priority source within the level being acknowledged. In addition to providing the vector number directly
for the byte-sized IACK read, this 8-bit register is also loaded with information about the interrupt level
and priority being acknowledged. This register provides the association between the acknowledged
“physical” interrupt request number and the programmed interrupt level/priority. The contents of this
read-only register are described in
7
6
5
4
3
2
1
0
R
IRQ
0
W
Reset
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x718
Figure 13-7. Interrupt Request Level Register (IRLR)
Table 13-9. IRQn Field Descriptions
Bits
Name
Description
7–1
IRQ
Interrupt requests. Represents the prioritized active interrupts for each level.
0 There are no active interrupts at this level
1 There is an active interrupt at this level
0
—
Reserved
7
6
5
4
3
2
1
0
R
—
LEVEL
PRI
W
Reset
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x719
Figure 13-8. IACK Level and Priority Register (IACKLPR)
Table 13-10. IACKLPR Field Descriptions
Bits
Name
Description
7
—
Reserved