5 fbcs register (pddr_fbcs), 3 port x pin data/set data registers (ppdsdr_x), Port – Freescale Semiconductor MCF5480 User Manual

Page 386: Figure 15-10, Figure 15-11, Ci2c), Displays the 4-bit pddr, 3 port x pin data/set data registers (ppdsdr_ x )

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MCF548x Reference Manual, Rev. 3

15-14

Freescale Semiconductor

15.3.2.2.5

FBCS Register (PDDR_FBCS)

The 5-bit PDDR_FBCS register is for data direction of PFBCSn.

Figure 15-11

displays the 5-bit

PDDR_FBCS register.

15.3.2.3

Port x Pin Data/Set Data Registers (PPDSDR_x)

The PPDSDR registers reflect the current pin states and control the setting of output pins when the pin is

configured for general purpose I/O.

7

6

5

4

3

2

1

0

R

0

0

0

0

DDx3

DDx2

DDx1

DDx0

W

Reset

0

0

0

0

0

0

0

0

Reg

Addr

MBAR + 0xA12 (PDDR_DMA), 0xA18 (PDDR_FECI2C)

Figure 15-10. 4-Bit PDDR_DMA and PDDR_FECI2C Registers

Table 15-12. 4-Bit PDDR_DMA and PDDR_FECI2C Field Descriptions

Bits

Name Description

7–4

Reserved, should be cleared

3–0

DDxn

PDDR_DMA and PDDR_FECI2C Data Direction
0 PDMAn or PFECI2Cn pin is configured as input
1 PDMAn or PFECI2Cn pin is configured as output

7

6

5

4

3

2

1

0

R

0

0

DDFB5

DDFB4

DDFB3

DDFB2

DDFB1

0

W

Reset

0

0

0

0

0

0

0

0

Reg

Addr

MBAR + 0xA11 (PDDR_FBCS)

Figure 15-11. 5-Bit PDDR_FBCS Register

Table 15-13. 5-Bit PDDR_FBCS Field Descriptions

Bits

Name Description

7–6

Reserved, should be cleared

5–1

DDFBn

PDDR_FBCS data direction
0 PFBCSn pin is configured as input
1 PFBCSn pin is configured as output

0

Reserved, should be cleared

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