Freescale Semiconductor MCF5480 - Manual (Page 424)

MCF548x Reference Manual, Rev. 3
17-8 Freescale Semiconductor
1 The access column indicates whether the corresponding register allows both read/write functionality (R/W), read-only
functionality (R), or write-only functionality (W). A read access to a write-only register returns zeros. A write access to a
read-only register has no effect.
2 Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved
address spaces and reserved register bits have no effect.
17.5.2.1 Chip-Select Address Registers (CSAR0–CSAR5)
CSARn, Figure 17-3 , specify the chip-select base addresses.
0x052C Chip-select control register—bank 3 (CSCR3) 0x0000_0000 R/W
0x0530 Chip-select address register—bank 4 (CSAR4) 0x0000_0000 R/W
0x0534 Chip-select mask register—bank 4 (CSMR4) 0x0000_0000 R/W
0x0538 Chip-select control register—bank 4 (CSCR4) 0x0000_0000 R/W
0x053C Chip-select address register—bank 5 (CSAR5) 0x0000_0000 R/W
0x0540 Chip-select mask register—bank 5 (CSMR5) 0x0000_0000 R/W
0x0544 Chip-select control register—bank 5 (CSCR5) 0x0000_0000 R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R BA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x500 (CSAR0); 0x50C (CSAR1); 0x518 (CSAR2);
0x524 (CSAR3); 0x530 (CSAR4); 0x53C (CSAR5)
Figure 17-3. Chip-Select Address Registers (CSARn)
Table 17-7. CSARn Field Descriptions
Bits Name Description
31–16 BA Base address. Defines the base address for memory dedicated to chip-select FBCSn. BA is
compared to bits 31–16 on the internal address bus to determine if chip-select memory is being
accessed.
15–0 — Reserved, should be cleared
Table 17-6. Chip-Select Registers (Continued)
Register
Offset
[31:24] [23:16] [15:8] [7:0] ResetValue Access
1