Freescale Semiconductor MCF5480 - Manual (Page 442)

MCF548x Reference Manual, Rev. 3
17-26 Freescale Semiconductor
Figure 17-26. Write Cycle with Two Clock Address Setup and
Two Clock Hold (One Wait State)
17.6.6 Burst Cycles
The MCF548x can be programmed to initiate burst cycles if its transfer size exceeds the size of the port it
is transferring to. The initiation of a burst cycle is encoded on the size pins. For burst transfers to smaller
port sizes, TSIZ[1:0] indicate the size of the entire transfer. For example, with bursting enabled, a word
transfer to an 8-bit port would take a 2-byte burst cycle, for which TSIZ[1:0] = 10 throughout. A longword
transfer to an 8-bit port would take a 4-byte burst cycle, for which TSIZ[1:0] = 00 throughout.
With bursting disabled, any transfer is larger than port size is broken into multiple individual transfers.
With bursting enabled, an access is larger than port size would result a burst cycle of multiple beats.
Table 17-12 shows the result of such transfer translations.
The MCF548x bus can support 3-1-1-1 burst cycles and optimize DMA transfers. A user can add wait
states by delaying termination of the cycle. If internal termination is used, different wait state counters can
be used for the first access and the following beats.
Table 17-12. Transfer Size and Port Size Translation
Port Size PS[1:0]
Transfer Size
TSIZ[1:0]
Burst-inhibited: number of transfers
Burst enabled: number of beats
01 (8-bit) 10 (word) 2
00 (longword) 4
11 (line) 16
1- (16-bit) 00 (longword) 2
11 (line) 8
00 (32-bit) 11 (line) 4
CLK
AD[ X:0]
AD[31:Y]
R/W
ALE
TA
OE
S0 AS S1 WS S2 S3 AH
FBCSn, BE/BWEn
ADDR[X:0]
DATA
TSIZ[1:0] TSIZ[1:0]
A[31:Y]