7 misaligned operands, Misaligned operands -31, Figure 17-34 – Freescale Semiconductor MCF5480 User Manual

Page 447

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Functional Description

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor

17-31

Figure 17-34. Longword Write Burst to 8-Bit Port 4-1-1-1 (Address Setup and Hold)

17.6.7

Misaligned Operands

Because operands, unlike opcodes, can reside at any byte boundary, they are allowed to be misaligned. A

byte operand is properly aligned at any address, a word operand is misaligned at an odd address, and a

longword is misaligned at an address not a multiple of four. Although the MCF548x enforces no alignment

restrictions for data operands (including program counter (PC) relative data addressing), additional bus

cycles are required for misaligned operands.
Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch

a misaligned instruction word causes an address error exception.
The MCF548x converts misaligned, cache-inhibited operand accesses to multiple aligned accesses.

Figure 17-35

shows the transfer of a longword operand from a byte address to a 32-bit port. First a byte is

transferred at an offset of 0x1. The slave device supplies the byte and acknowledges the data transfer.

When the MCF548x starts the second cycle, a word is transferred with a byte offset of 0x2. The next two

bytes are transferred in this cycle. In the third cycle, byte 3 is transferred. The byte offset is now 0x0, the

port supplies the final byte, and the operation is complete.

Figure 17-35. Example of a Misaligned Longword Transfer (32-Bit Port)

If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the

cache. The example in

Figure 17-36

differs from the one in

Figure 17-35

because the operand is

word-sized and the transfer takes only two bus cycles.

CLK

AD[23:0]

AD[31:24]

R/W

ALE

TSIZ[1:0]

TA

TBST

S0

AS

S1

S2

S2

S2

S2

S3

AH

OE

ADDR[23:0]

A[31:24]

DATA

DATA

DATA

FBCSn, BE/BWEn

11

DATA

––

Byte 0

––

––

Transfer 1

––

––

Byte 1

Byte 2

Byte 3

––

––

––

Transfer 2

Transfer 3

001

010

100

16 15

31

0

24 23

7

8

A[2:0]

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