Freescale Semiconductor MCF5480 - Manual (Page 454)

MCF548x Reference Manual, Rev. 3
18-6 Freescale Semiconductor
18.4.2 SDRAM SDR Connections
Figure 18-2 shows a block diagram of the connections between the MCF548x and SDR SDRAM
components. SDR design requires special timing consideration for the SDDQS[3:0] signals. For reads
from DDR SDRAMs, the memory will drive the DQS pins so that the data lines and DQS signals have
concurrent edges. The MCF548x SDRAMC is designed to latch data 1/4 clock after the SDDQS[3:0] edge.
For DDR SDRAM, this ensures that the latch time is in the middle of the data valid window.
The SDRAMC also uses the SDDQS[3:0] signals to determine when read data can be latched for SDR
SDRAM; however, SDR memories do not provide DQS outputs. Instead the SDRAMC provides an
SDRDQS output that is routed back into the controller as SDDQS[3:0]. The SDRDQS signal should be
routed such that the valid data from the SDRAM reaches the MCF548x at the same time or just before the
SDRDQS reaches the SDDQS[3:0] inputs. When routing SDRDQS the outbound trace length should be
matched to the SDCLK trace length. This will align SDRDQS to the SDCLK as if the memory had
generated the DQS pulse. The inbound trace should be routed along the data path. This should synchronize
the SDDQS so that the data is latched in the middle of the data valid window.
Figure 18-2. MCF548x Connections to SDR SDRAM
18.4.3 SDRAM DDR Component Connections
Figure 18-3 shows a block diagram of the connections between the MCF548x and DDR SDRAM
components.
MCF548X SDR SDRAM
SDADDR[12:0]
SDDATA[31:0]
SDBA[1:0]
SDCSn
RAS
CAS
SDWE
SDCKE
SDCLK[1:0] CLK
CKE
CS
RAS
CAS
WE
DQM[3:0]
BA[1:0]
A[12:0]
DQ[31:0]
SDDM[3:0]
SDRDQS
SDDQS[3:0]