Freescale Semiconductor MCF5480 - Manual (Page 462)

MCF548x Reference Manual, Rev. 3
18-14 Freescale Semiconductor
18.5.2.1 SDR Initialization
SDR initialization requires the following steps:
1. After reset is deactivated, pause for the amount of time indicated in the SDRAM specification.
Usually 100 µs or 200µs.
2. Initialize the SDRAM drive strength (SDRAMDS) and SDRAM chip select configuration
(CSnCFG) registers.
3. Program the SDRAM configuration registers (SDCFG1 and SDCFG2) with the correct delay and
timing values.
4. Issue a PALL command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL] set.
The SDCR[MODE_EN, REF, and IREF] bits should all remain cleared for this step.
5. Refresh the SDRAM. The SDRAM spec should indicate a number of refresh cycles to be
performed before issuing an LMR command. Write to the SDCR with the IREF bit set
(SDCR[MODE_EN, REF, and IPALL] should be cleared). This will force a refresh of the
SDRAM each time the IREF bit is set. Repeat this step until the specified number of refresh
cycles have completed.
6. Set SDCR[REF] to enable automatic refreshing for the rest of the initialization and regular
operation. SDCR[MODE_EN, REF, and IPALL] remain cleared.
7. Initialize the SDRAM’s mode register using the LMR command. See Section 18.5.1.5, “Load
Mode/Extended Mode Register Command (LMR, LEMR) ” for more instruction on issuing an
LMR command.
18.5.2.2 DDR Initialization
The steps for DDR initialization are similar to the SDR initialization sequence; however, there are some
additional steps required for DDR:
1. After reset is deactivated, pause for the amount of time indicated in the SDRAM specification.
Usually 100 µs or 200µs.
2. Initialize the SDRAM drive strength (SDRAMDS) and SDRAM chip select configuration
(CSnCFG) registers.
3. Program the SDRAM configuration registers (SDCFG1 and SDCFG2) with the correct delay and
timing values.
4. Issue a PALL command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL] set.
The SDCR[REF, and IREF] bits should remain cleared for this step.
5. Initialize the SDRAM’s extended mode register to enable the DLL. See Section 18.5.1.5, “Load
Mode/Extended Mode Register Command (LMR, LEMR) ” for instructions on issuing an LEMR
command.
6. Initialize the SDRAM’s mode register and reset the DLL using the LMR command. See
Section 18.5.1.5, “Load Mode/Extended Mode Register Command (LMR, LEMR) ” for more
instruction on issuing an LMR command. During this step the OP_MODE field of the mode
register should be set to “normal operation/reset DLL.”
7. Pause for the DLL lock time specified by the memory.