4 tx enables register (pciter) – Freescale Semiconductor MCF5480 User Manual
Page 510
MCF548x Reference Manual, Rev. 3
19-26
Freescale Semiconductor
19.3.3.1.4
Tx Enables Register (PCITER)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
RC
RF
0
CM
BE
0
0
ME
0
0
FEE
SE
RE
TAE
IAE
NE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x840C
Figure 19-23. Tx Enables Register (PCITER)
Table 19-22. PCITER Field Descriptions
Bits
Name
Description
31
RC
Reset controller. User writes this bit high to put Transmit Controller in a reset state. Other register
bits are not affected. This Reset is intended for recovery from an error condition or to reload the
Start Address when Continuous mode is selected. This Reset bit does not prohibit register access
but it must be negated in order to initiate a Restart sequence (i.e. writing the Packet_Size register).
If it is used to reload a Start Address then the Start_Add register must be written prior to
deasserting this Reset bit.
30
RF
Reset FIFO. The FIFO will be reset and flushed of any existing data when set high. The Reset
Controller bit and the Reset FIFO bit operate independently but clearly both must be low for normal
operation.
29
—
Reserved, should be cleared.
28
CM
Continuous mode. User writes this bit high to activate Continuous mode. In Continuous mode the
Start_Add value is ignored at each packet restart and the PCI address is auto-incremented from
one packet to the next. Also, the Packets_Done status byte will become active, indicating how
many packets have been transmitted since the last Reset Controller condition. If the Continuous
bit is low, software is responsible for updating the Start_Add value at each packet Restart.
27
BE
Bus error enable. User writes this bit high to enable bus error indications. Setting this bit allows the
errors indicated by BE1, BE2, and BE3 in PCITSR to generate a bus error, which can result in a
TEA on the XL bus. See
Section 19.3.3.1.8, “Tx Status Register (PCITSR),”
for bus error
descriptions. Normally this bit will be low (negated) since illegal slave bus accesses are not
destructive to register contents (although it may indicate broken software). This bit does not affect
interrupt generation.
26–25
—
Reserved, should be cleared.
24
ME
Master enable. This is the Transmit Controller master enable signal. User must write it high to
enable operation. It can be toggled low to permit out-of-order register updates prior to generating
a Restart sequence (in which case transmission will begin when Master Enable is written back
high), but it should not be used as such in Continuous mode because it can have the side effect of
resetting the Packets_Done status counter.
23–22
—
Reserved, should be cleared.