Freescale Semiconductor MCF5480 - Manual (Page 540)

MCF548x Reference Manual, Rev. 3
19-56 Freescale Semiconductor
Figure 19-52. Initiator Arbitration Block Diagram
19.4.2.1 Priority Scheme
The PCI initiator arbiter uses the following fixed priority scheme:
1. XL bus initiator
2. Comm bus transmit (Tx)
3. Comm bus receive (Rx) (lowest)
19.4.3 Configuration Interface
The PCI bus protocol requires the implementation of a standardized set of registers for most devices on
the PCI bus. The MCF548x implements a Type 0 Configuration register set or header. These registers,
discussed in Section 19.3.1, “PCI Type 0 Configuration Registers,” are primarily intended to be read or
written by the PCI configuring master at initialization time through the PCI bus. The MCF548x provides
internal access to these registers through a slave bus interface. As with most MCF548x registers, they are
accessible by software in the address space at offsets of MBAR. Internal accesses to the Type 0
Configuration header do not require PCI arbitration when they are accessed as offsets of MBAR and are
allowed to execute regardless of whether any write data is posted in the PCI Controller.
If the MCF548x is the configuring master, the slave bus interface should be used to configure the PCI
Controller. An external master would configure the PCI controller through the external PCI bus.
More information on the standard PCI Configuration register can be found in the PCI 2.2 specification.
19.4.4 XL Bus Initiator Interface
The processor core or internal masters may access the PCI bus via the XL bus initiator interface. This
internal interface is accessed through three windows in MCF548x address space set up by base address and
base address mask registers ( Section 19.3.2.5, “Initiator Window 0 Base/Translation Address Register
(PCIIW0BTAR)” ). The base address registers must be enabled by setting their respective enable bits in
the Section 19.3.2.8, “Initiator Window Configuration Register (PCIIWCR).” Accesses to this area are
translated into PCI transactions on the PCI bus. See Section 19.5.2, “Address Maps,” for examples on
setting up address windows.
rx_req
rx_gnt
tx_gnt
tx_req
PCI
Request/Grant
(to PCI Arbiter)
External
PCI Bus
PCI
Initiator
Arbiter
Comm Bus
Initiator
XL Bus
Initiator XL Bus
Arbiter
Multichannel
DMA
Controller
PCI
Controller
Initiator
Interface