Freescale Semiconductor MCF5480 - Manual (Page 552)

MCF548x Reference Manual, Rev. 3
19-68 Freescale Semiconductor
19.4.6.3 Data Translation
The PCI bus is inherently little endian in its byte ordering. The comm bus however is big endian.
Table 19-55 shows the byte lane mapping between the two buses. Because this interface only allows 32-bit
accesses, there is only one entry.
19.4.6.4 Initialization
The following list is the recommended procedure for setting up either the Transmit or Receive controller.
1. Set the Start Address
2. Set the PCI command, Max_Retries, and Max_Beats
3. Set mode, Continuous or Non-continuous
4. Reset the FIFO
5. Set the FIFO Alarm and Granularity fields
6. Set the Master Enable bit
7. Set the Reset Controller bit low
8. Write the Packet Size value to begin the transfer
19.4.6.5 Restart and Reset
This section describes Restart and Reset operation for both the Transmit and Receive controllers of the
communications subsystem interface.
A Restart sequence is required whenever the controller ends a packet transmission, either normally or
abnormally. In non-continuous mode, a new Start_Add value is generally required since this value is
re-used as the start of the next packet once it is Restarted. In Continuous mode, the Start_Add value is not
reused. Instead, the next packet begins where the last one left off, but a Restart sequence is still required
to get this next packet started.
Writing a non-zero value to the Packet_Size register generates a Restart pulse to the controller. If the
Master Enable bit is low when the Packet_Size register is written, the Restart pulse will occur when the
Master Enable bit is programmed high. Depending on the desired mode of operation other register accesses
may be required, as described in the following paragraphs.
If Continuous mode is not selected, operation is fairly straight forward. Upon packet termination, Restart
will not occur until Packet_Size is written with a non-zero value, even if the packet size is the same it must
be re-written. The Master Enable bit was previously high and can remain so. The Reset Controller bit was
previously low and can remain so. Toggling the Master Enable or Reset bit is unnecessary but would not
disrupt the transmit controller. If any other Control values, e.g. Start_Add, are to be changed they should
be written either prior to writing the Packet_Size value or written while the Master Enable bit is negated
and the Reset Controller bit is negated. The recommended approach is to write the control values in order
(Packet_Size must be last) and not toggle the Master Enable bit. The Reset bit should remain negated.
Table 19-55. Comm Bus to PCI Byte Lanes for Memory Transactions
Transfer
Comm Bus PCI Data Bus
cAddress
[1:0]
cByte
Enable
[3:0]
Data Bus
PCIAD
[1:0]
BE
[3:0]
Data Bus
31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0
long 00 1111 OP0 OP1 OP2 OP3 00 0000 OP3 OP2 OP1 OP0