Freescale Semiconductor MCF5480 - Manual (Page 569)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 20-9
Figure 20-6. Higher Priority Override
The arbiter again deasserts device 2’s GNT on clock 2, but device 2 initiates a transaction in the same
cycle. As long as the PCI bus is idle and GNT is asserted, a master can begin a transaction on the next
cycle. (Assertion of REQ is not required.)
Next access is again awarded to device 0 and upon detection of an idle PCI state, it performs its transaction
(clocks 5 and 6). Because it has subsequent transactions to perform, device 0 leaves its REQ asserted. Like
the previous timing diagram, PCI bus ownership switches to device 1.
While device 1 is performing a transaction on the PCI bus on clock 8, device 0 is the only device still
requesting subsequent use of the bus. In the next cycle, the arbiter asserts GNT to device 0 in response to
the request. Device 2, during that same cycle, asserts its REQ. The arbiter, because access 1 is still in
progress, determines that device 2 is higher priority than device 0 (after device 1 access), rearbitrates and
deasserts GNT to device 0 and asserts GNT to device 2 in the next cycle (clock 10).
20.4.3 Master Time-Out
A master is considered “broken” if it has not initiated an access (dropped PCIFRAME) after its GNT has
been asserted (its REQ is also asserted) and the bus is in the idle state for 16 clocks. A 16 clock (PCI clock)
timer is instituted to prevent arbitration lock-up for this case. When the timer expires, the arbiter removes
the GNT from the device and gives the bus to the master with the next highest priority. Subsequent requests
from the timed-out master will be ignored until its REQ is negated for at least one clock cycle.
A status bit is set when any master times out. If the corresponding interrupt enable bit is set, a CPU
interrupt will assert. Software can query the status bits to detect a “broken” master in the PCI system. (See
Section 20.3.2, “PCI Arbiter Status Register (PASR) ”)
If a master does not initiate a transaction after its GNT has been asserted, but deasserts REQ before the 16
clock timer expires, the arbiter deasserts GNT and rearbitrates for the next transaction. The master is not
PCI_CLK
REQ[0]
REQ[1]
REQ[2]
GNT[0]
GNT[1]
PCIIRDY
PCIFRAME
PCIAD
0 1 2 3 4 5 6 7 8 9 10 11 12
GNT[2]
LOW DATA ADDR DATA ADDR DATA
Access 2 Access 0
STATE IDLE ACTIVE GRANT ACTIVE GRANT TURN
(Parked)
ADDR
Access 1
ADDR DATA
Access 2
GRANT ACTIVE ACTIVE