Freescale Semiconductor MCF5480 - Manual (Page 570)

MCF548x Reference Manual, Rev. 3
20-10 Freescale Semiconductor
considered “broken” and subsequent requests are acknowledged. This “never-mind” scenario is
detrimental to system performance, however, and is not a recommended implementation.
20.5 Reset
Reset capability is provided by the MCF548x system reset. This signal resets both hardware and software
registers in the internal PCI arbiter.
An MCF548x software bit external to the arbiter controls the external PCIRESET signal (See
Section 19.3.2.1, “Global Status/Control Register (PCIGSCR)” ). During the MCF548x system reset, this
bit is set and PCIRESET is asserted. No PCI traffic is allowed during this time. Only a software write of
zero brings the PCI bus out of reset.
Because the external PCI GNT signals must tristate during PCI reset, the PCIRESET output signal is used
as an output enable (active high) for all PCIGNT outputs.
20.6 Interrupts
Only a detection of a malfunctioning master can generate a CPU interrupt from the PCI arbiter module.
(see Section 20.4.3, “Master Time-Out ”). If a master time-out occurs and its interrupt enable bit is set, a
level high will be driven onto the interrupt signal output of the arbiter. The interrupt will deassert when
either PASR[EXTMBK], the time-out status bit, or PASR[ITLMBK], the interrupt enable control bit, is
cleared.
When a master time-out occurs and the corresponding status bit is set, software must write a 1 to the bit
location to clear it. If the status bit generated an interrupt because the corresponding interrupt enable bit
was set, clearing the status bit is one way to deassert the interrupt output. An alternate way to force the
interrupt to a level low is to disable the interrupt enable that corresponds to the asserted status bit. The
status bit, however, remains set.