6 flexcan error and status register (errstat), Flexcan error and status register (errstat) -15 – Freescale Semiconductor MCF5480 User Manual
Page 585
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
21-15
to zero and counts in a manner where the internal counter counts 11 such bits, then wraps around
while incrementing the TXECTR. When TXECTR reaches the value of 128, the FLTCONF field
in the error and status register is updated to be error-active, and both error counters are reset to zero.
At any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the
internal counter resets itself to zero without affecting the TXECTR value.
•
If during system start-up, only one node is operating, then its TXECTR increases in each message
it is trying to transmit, as a result of acknowledge errors (indicated by the ACKERR bit in the error
and status register). After the transition to error-passive state, the TXECTR does not increment
anymore by acknowledge errors. Therefore the device never goes to the bus off state.
•
If the RXECTR increases to a value greater than 127, it is not incremented further, even if more
errors are detected while being a receiver. At the next successful message reception, the counter is
set to a value between 119 and 127 to resume to error-active state.
21.3.2.6
FlexCAN Error and Status Register (ERRSTAT)
ERRSTAT reflects various error conditions, some general status of the device, and is the source of three
interrupts to the host. The reported error conditions (bits 15:10) are those occurred since the last time the
host read this register. The read action clears bits 15-10. Bits 9–3 are status bits.
Most bits in this register are read only, except for BOFFINT, WAKINT, and ERRINT, which are interrupt
sources that can be cleared by writing 1 to them. Writing 0 has no effect. Refer to
.”
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
RXECTR
TXECTR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0xA01C (ERRCNT0); 0xA81C (ERRCNT1)
Figure 21-10. FlexCAN Error Counter Register (ERRCNT)