Freescale Semiconductor MCF5480 - Manual (Page 601)

FlexCAN Initialization Sequence
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 21-31
• If the RXECTR increases to a value greater than 127, it is no longer incremented, even if more
errors are detected while being a receiver. At the next successful message reception, the counter is
set to a value between 119 and 127, in order to return to error active state.
21.5 FlexCAN Initialization Sequence
Initialization of the FlexCAN includes the initial configuration of the message buffers and configuration
of the CAN communication parameters following a reset, as well as any reconfiguration which may be
required during operation. The following is a generic initialization sequence for the FlexCAN:
1. Initialize all operation modes
a) Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and RJW
in the FlexCAN control register (CANCTRL).
b) Select the S-clock rate by programming the PRESDIV register.
c) Select the internal arbitration mode (CANCTRL[LBUF]).
2. Initialize message buffers
a) The control/status word of all message buffers must be written either as an active or inactive
message buffer.
b) All other entries in each message buffer should be initialized as required.
3. Initialize mask registers for acceptance mask as needed
4. Initialize FlexCAN interrupt handler
a) Initialize the interrupt controller registers for any needed interrupts. See Chapter 13,
“Interrupt Controller,” for more information.
b) Set the required mask bits in the IMASK register (for all message buffer interrupts), in
CANCTRL (for bus off and error interrupts), and in CANMCR for the WAKE interrupt.
5. Clear the HALT bit in the module configuration register
a) At this point, the FlexCAN will attempt to synchronize with the CAN bus.
NOTE
In both the transmit and receive processes, the first action in preparing a
message buffer should be to deactivate the buffer by setting its CODE field
to the proper value. This requirement is mandatory to assure data coherency.
21.5.1 Interrupts
There are four interrupt sources for the FlexCAN module. A combined interrupt for all 16 MBs is
generated by combining all the interrupt sources from MBs. This interrupt gets generated when any of the
16 MB interrupt sources generates a interrupt. In this case, the CPU must read the IFLAG register to
determine which MB caused the interrupt. The other three interrupt sources (bus off, error, and wake-up)
act in the same way, and are located in the error and status register. The bus off and error interrupt mask
bits are located in the CANCTRL register, and the wake-up interrupt mask bit is located in the CANMCR.