Freescale Semiconductor MCF5480 - Manual (Page 604)

MCF548x Reference Manual, Rev. 3
22-2 Freescale Semiconductor
define the cryptographic function to be performed and the location of the data. The SEC’s bus-mastering
capability permits the host processor to set up a crypto-channel with a few register writes, then the SEC
can perform reads and writes on system memory to fetch data packet descriptors and complete the
specified tasks.
22.3 Block Diagram
Figure 22-1 shows a block diagram of the SEC module. The bus interface module is designed to transfer
32-bit words between the internal bus and any register inside the SEC.
Figure 22-1. SEC Block Diagram
A typical operation consists of the following steps:
• An operation begins with a write of a pointer to a crypto-channel fetch register that points to a data
packet descriptor.
• The channel requests the descriptor and decodes the operation to be performed.
• The channel then requests the controller to assign crypto execution units and fetch the keys,
context/initialization vectors (IVs), and data needed to perform the given operation.
• The controller satisfies the requests by assigning execution units to the channel and by making
requests to the master interface per the programmable priority scheme.
• As data is processed, it is written to the individual execution unit’s output FIFO and then back to
system memory via the bus interface.
22.4 Overview
22.4.1 Bus Interface
The bus interface manages communication between the SEC internal execution units and the internal bus.
The interface uses the bus master/slave protocols. All on-chip resources are memory mapped, and the
target accesses and initiator writes from the SEC must be addressed on longword boundaries. The SEC
will perform initiator reads on byte boundaries and will adjust the data (realign the data) to place on
longword boundaries as appropriate. Access to system memory is a critical factor in co-processor
performance, and the bus interface of the SEC core allows it to achieve performance unattainable on
secondary busses.
FIFO
Crypto-
channel
Crypto-
channel
Control
DEU
FIFO
FIFO
FIFO
FIFO
AFEU
Bus
Interface
AESU
FIFO
FIFO FIFO
RNG MDEU