5 data packet descriptor buffer (cdbufn), 8 arc four execution unit (afeu), 1 afeu register map – Freescale Semiconductor MCF5480 User Manual
Page 630: 2 afeu reset control register (afrcr), Data packet descriptor buffer (cdbufn) -28, Arc four execution unit (afeu) -28, Afeu register map -28, Afeu reset control register (afrcr) -28, P. 22-28, The fr, displayed in
MCF548x Reference Manual, Rev. 3
22-28
Freescale Semiconductor
describes the FRn fields.
22.7.1.5
Data Packet Descriptor Buffer (CDBUFn)
This bank of eight registers stores the header, followed by length/pointer pairs, followed by a next data
packet descriptor pointer. These registers fully describe the service the SEC is to perform. The header
indicates the precise service (Single-DES CBC encryption or generate random numbers are two
examples), and the length/pointer pairs indicate the number and location of data and context information
needed to complete the service.
22.8
ARC Four Execution Unit (AFEU)
This section contains details about the ARC Four Execution Unit (AFEU), including register details.
22.8.1
AFEU Register Map
The registers used in the AFEU are documented primarily for debug and target mode operations. The
AFEU contains the following registers:
•
Reset control register
•
Status register
•
Interrupt status register
•
Interrupt mask register
22.8.2
AFEU Reset Control Register (AFRCR)
This register, as shown in
, allows three levels of reset that effect the AFEU only, as defined
by three self-clearing bits. It should be noted that the AFEU executes an internal reset sequence for
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
FETCH_ADDR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
FETCH_ADDR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x2204C (FR0), 0x2304C (FR1)
Figure 22-20. Fetch Register (FRn)
Table 22-17. FRn Field Descriptions
Bits
Name
Description
31–0
FETCH
ADDR
Fetch address. Pointer to system memory location of a descriptor the host wants the SEC to fetch.