4 deu interrupt status register (disr), Deu interrupt status register (disr) -37, P. 22-37 – Freescale Semiconductor MCF5480 User Manual
Page 639
Data Encryption Standard Execution Units (DEU)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
22-37
22.9.4
DEU Interrupt Status Register (DISR)
The DEU interrupt status register, shown in
, tracks the state of possible errors, if those errors
are not masked, via the DEU interrupt mask register.
Figure 22-27. DEU Interrupt Status Register (DISR)
describes DEU interrupt register signals.
25
ID
Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the
controller interrupt status register (
Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and
0 DEU is not signaling done
1 DEU is signaling done
24
RD
Reset done. This status bit, when high, indicates that DEU has completed its reset sequence, as
reflected in the signal sampled by the appropriate crypto-channel.
0 Reset in progress
1 Reset done
23–0
—
Reserved
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
ME
AE
OFE
IFE
0
IFO
OFU
0
0
0
KPE
IE
ERE
CE
KSE
DSE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x2A030
Table 22-24. DISR Field Descriptions
Bits
Name
Description
31
ME
Mode error. An illegal value was detected in the mode register. Note: writing to reserved bits in mode
register is likely source of error.
0 No error detected
1 Mode error
30
AE
Address error. An illegal read or write address was detected within the DEU address space.
0 No error detected
1 Address error
Table 22-23. DSR Field Descriptions (Continued)
Bits
Name
Description