Freescale Semiconductor MCF5480 - Manual (Page 65)

MCF548x Family Features
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 1-7
boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into
one shift register. Test logic, implemented using static logic design, is independent of the device system
logic. The MCF548x implementation can do the following:
• Perform boundary scan operations to test circuit board electrical continuity
• Sample MCF548x system pins during operation and transparently shift out the result in the
boundary scan register
• Bypass the MCF548x for a given circuit board test by effectively reducing the boundary-scan
register to a single bit
• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels
1.4.4 On-Chip Memories
1.4.4.1 Caches
There are two independent caches associated with the ColdFire V4e core complex: a 32-Kbyte instruction
cache and a 32-Kbyte data cache. Caches improve system performance by providing single-cycle access
to the instruction and data pipelines. This decouples processor performance from system memory
performance , increasing bus availability for on-chip DMA or external devices.
1.4.4.2 System SRAM
The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access
in a single cycle. The location of the memory block can be set to any 32-Kbyte address boundary within
the 4-Gbyte address space. The memory is ideal for storing critical code or data structures, for use as the
system stack, or for storing FEC data buffers. Because the SRAM module is physically connected to the
processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing
commands from the debug module.
The SRAM module is also accessible by multiple non-core bus masters, such as the DMA controller, the
encryption accelerator, and the PCI Controller.
1.4.5 PLL and Chip Clocking Options
MCF548x products contain an on-chip PLL capable of accepting input frequencies from 30–66.66 MHz.
Table 1-2 contains the frequencies of the system buses for the members of the MCF548x family under
various core/SDRAM/PCI/Flexbus clocking options.
Table 1-2. MCF548x Family Clocking Options
Core
(MHz)
Internal XLB, SDRAM
Bus, and PSTCLK
Frequency (MHz)
CLKIN—PCI and FlexBus
Frequency (MHz)
Clock Ratio
120.0–200 60.0–100 30.0–50.0 1:2