Freescale Semiconductor MCF5480 - Manual (Page 712)

MCF548x Reference Manual, Rev. 3
23-4 Freescale Semiconductor
23.2.1.5 Test Reset/Development Serial Clock (TRST/DSCLK)
The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces the
TAP controller to the test-logic-reset state.
The DSCLK pin clocks the serial communication port to the debug module. Maximum frequency is 1/5
the processor clock speed. At the rising edge of DSCLK, the data input on DSI is sampled and DSO
changes state.
23.2.1.6 Test Data Output/Development Serial Output (TDO/DSO)
The TDO pin is the LSB-first data output. Data is clocked out of TDO on the falling edge of TCK. TDO
is tri-stateable and is actively driven in the shift-IR and shift-DR controller states.
The DSO pin provides serial output data in BDM mode.
23.3 Memory Map/Register Definition
23.3.1 Memory Map
The JTAG module registers are not memory mapped and are only accessible through the TDO/DSO pin.
23.3.2 Register Descriptions
All registers are shift-in and parallel load.
23.3.2.1 Instruction Shift Register (IR)
The JTAG module uses a 4-bit shift register with no parity. The IR transfers its value to a parallel hold
register and applies an instruction on the falling edge of TCK when the TAP state machine is in the
update-IR state. To load an instruction into the shift portion of the IR, place the serial data on the TDI pin
before each rising edge of TCK. The MSB of the IR is the bit closest to the TDI pin, and the LSB is the bit
closest to the TDO pin.
23.3.2.2 IDCODE Register
The IDCODE is a read-only register; its value is chip dependent. For more information, see
Section 23.4.3.2, “IDCODE Instruction .”