6 timing diagrams, 1 level-triggered requests, 2 edge-triggered requests – Freescale Semiconductor MCF5480 User Manual
Page 750: Timing diagrams -30, Level-triggered requests -30, Edge-triggered requests -30
MCF548x Reference Manual, Rev. 3
24-30
Freescale Semiconductor
24.6
Timing Diagrams
The following timing diagrams show the three modes of external request operation.
24.6.1
Level-Triggered Requests
shows the timing for level-triggered external requests. For level-triggered requests, the
internal DMA request will assert when DREQ is detected low. The active high internal DMA request is
asserted on the rising edge of clock 2 after DREQ is detected low. When the DMA transfer completes, the
active high internal acknowledge is asserted (clock 4). This causes the external DACK to assert, and the
internal DMA request is negated. Since DREQ remains asserted an new internal request is signalled on the
rising edge of clock 6.
.
Figure 24-24. Level-Triggered External Request Timing
24.6.2
Edge-Triggered Requests
shows the timing for level-triggered external requests. For level-triggered requests, the
internal DMA request will assert when there is a falling edge of the DREQ signal. The active high internal
DMA request is asserted on the rising edge of clock 2 after the falling edge of DREQ. When the DMA
transfer completes, the active high internal acknowledge is asserted (clock 4). This causes the external
3
I
Integer Mode
0 Fractional data representation
1 Integer data representation
2
SP
Speculative Prefetch
0 Do not enable speculative prefetch
1 Enable speculive prefetch
1
CW
Combined Write Enable
0 Do not enable combined writes
1 Enable combined writes
0
RL
Read Line Buffer Enable
0 Do not enable line reads
1 Enable line reads
Table 24-20. Behavior of Task Table Control Bits (Continued)
Bit
Name
Function
CLK
DREQ
Internal DMA
Internal DMA
DACK
1
2
3
4
5
6
7
8
9
10
0
Request
Acknowledge