4 clock select register (psccsrn), Clock select register (psccsrn) -10, 4 clock select register (psccsr n ) – Freescale Semiconductor MCF5480 User Manual
Page 772
MCF548x Reference Manual, Rev. 3
26-10
Freescale Semiconductor
26.3.3.4
Clock Select Register (PSCCSRn)
The comm timers (CTMs) or the PSC’s timer (see
Section 26.3.3.11, “Counter Timer Registers
” for more information) can be used to generate the baud rate for UART and
SIR modes. The PSCCSR selects which clock input is used to generate the baud rate. The system clock
can be selected or the output from one of the comm timers (CTM) can be selected. If the CTM clock is
selected, it can be divided by 1 or 16. Please refer to the
Chapter 25, “Comm Timer Module (CTM),”
for
more information on the clock sources for baud rate generation.
shows the clock options for generating the baud rate for UART or SIR modes.
Figure 26-5. UART and SIR Baud Rate Clocking Sources
9
FU
For all modes, this field signifies that the RxFIFO is full.
0 The number of data in the RxFIFO is less than the threshold or the number of data is more than
the granularity after exceeding the threshold.
1 The number in RxFIFO is more than the threshold. This bit becomes low after reading enough
data from RxFIFO and the number in it becomes less than the granularity.
8
RXRDY
For all modes, this field signifies a Receiver ready.
0 There is no data in the RxFIFO.
1 There is at least one data in the RxFIFO.
7
CDE_DEOF
In UART mode, this bit is reserved.
In modem and SIR mode, this bit is reserved.
In MIR and FIR mode, this bit signifies Detect End of Frame or the RxFIFO contains EOF.
0 The receiver has not received an EOF after the last read PSCSR command and there is no EOF
in the FIFO.
1 The receiver has received an EOF since last PSCSR read or there is at least one EOF in the
RxFIFO. In this case, the interrupt and request can be asserted even if the number of the RxFIFO
is less than the threshold and PSCMR1[6]=1. This bit is also set if an error occurred and no
correct EOF is received.
6
ERR
Error bit. OR of all errors status bits including FIFO errors.
0 No error was detected.
1 At least one error occurred
5 - 0
—
Reserved
Table 26-5. PSCSRn Field Descriptions (Continued)
Bits
Name
Description
Comm
×1
Prescaler
×16
Prescaler
Clock
Generator
16-Bit
Divider
×32
Prescaler
TCSEL or RCSEL
Timern
Baud Rate
Internal
Bus
Clock