Freescale Semiconductor MCF5480 - Manual (Page 806)

MCF548x Reference Manual, Rev. 3
26-44 Freescale Semiconductor
are unaffected, and PSCSRn[ERR] sets when the receiver detects the start bit of the new overrunning
character.
To support flow control, the receiver can be programmed to automatically negate and assert RTS. In which
case, the receiver automatically negates RTS when a valid start bit is detected and the FIFO stack is full.
The receiver asserts RTS when a FIFO position becomes available.
Overrun errors can be prevented by connecting RTS to the CTS input of the transmitting device.
NOTE
The receiver can still read characters in the FIFO stack if the receiver is
disabled. If the receiver is reset, the FIFO stack, RTS control, all receiver
status bits, and interrupt requests are reset. No more characters are received
until the receiver is re-enabled.
Figure 26-41. PSC FIFO System
26.4.9.1 RX FIFO
The RX FIFO space is 512 bytes. For an Rx FIFO, the alarm value is not the amount of data in the Rx
FIFO. Instead, an interrupt occurs as a result of the amount of empty space remaining in the Rx FIFO.
These facts are described in Figure 26-41 .
If it is known how much data is needed in the Rx FIFO to cause an interrupt, the value that must be written
into the alarm register is the FIFO size minus the number of data bytes in the FIFO
Unlike the alarm value, granularity value represents a number of data bytes, not empty space.
empty
FIFO space
last byte to send
first byte to send
Granularity
Level
(value multplied by 4)
(example: 0x005)
Address:
0x1FF
Alarm Level
“almost empty”
(example: 0x010)
0x0
0x0
0x1FF
Transmitter
Tx Line
empty
FIFO space
last received byte
first received byte
Receiver
Rx Line
Granularity
Level
(value multplied by 4)
(example: 0x004)
Alarm Level
“almost full”
(example: 0x008)
Internal Bus Interface