Freescale Semiconductor MCF5480 - Manual (Page 842)

MCF548x Reference Manual, Rev. 3
27-24 Freescale Semiconductor
Eqn. 27-7
Table 27-18 shows an example of how to compute the delay after transfer.
27.7.3.5 Peripheral Chip Select Strobe Enable (PCSS)
The PCSS signal provides a delay to allow the DSPICSn signals to settle after transitioning, thereby
avoiding glitches. When the DSPI is in master mode and DMCR[PCSSE] bit is set, PCSS provides a signal
for an external demultiplexer to decode the DSPICSn[0,2:3] signals into as many as eight glitch-free
DSPICSn signals. Figure 27-14 shows the timing of the PCSS signal relative to PCS signals.
Figure 27-14. Peripheral Chip Select Strobe Timing
The delay between the assertion of the DSPICSn signals and the assertion of PCSS is selected by the
PCSSCK field in the DCTARn based on the following formula:
Eqn. 27-8
At the end of the transfer the delay between PCSS negation and DSPICSn negation is selected by the PASC
field in the DCTARn based on the following formula:
Eqn. 27-9
Table 27-19 shows an example of how to compute the t
pcssck
delay.
Table 27-20 shows an example of how to compute the t
pasc
delay.
NOTE
The PCSS signal is not supported when continuous DSPISCK is enabled
(CONT=1).
Table 27-18. Delay after Transfer Computation Example
PDT Prescaler DT Scaler Fsys Delay after Transfer
0b01 3 0b1110 32768 100 MHz 0.98 ms
Table 27-19. Peripheral Chip Select Strobe Assert Computation Example
PCSSCK Prescaler Fsys Delay before Transfer
0b11 7 100 MHz 70.0 ns
Table 27-20. Peripheral Chip Select Strobe Negate Computation Example
PASC Prescaler Fsys Delay after Transfer
0b11 7 100 MHz 70.0 ns
t
DT
1
f
sys
-------- PDT × DT × =
PCSS
DSPICS n
t
PCSSCK
t
PASC
t
PCSSCK
1
f
sys
-------- PCSSCK × =
t
PASC
1
f
sys
-------- PASC Ч =