Freescale Semiconductor MCF5480 - Manual (Page 848)

MCF548x Reference Manual, Rev. 3
27-30 Freescale Semiconductor
(t
DT
) is not inserted between the transfers. Figure 27-20 shows the timing diagram for two 4-bit transfers
with CPHA = 1 and CONT = 1.
Figure 27-20. Example of Continuous Transfer (CPHA = 1, CONT = 1)
Switching DCTARn registers between frames while using continuous selection can cause errors in the
transfer. The DSPICSn signal must be negated before DCTARn is switched.
When the CONT bit = 1 and the DSPICSn signals for the next transfer are different from the present
transfer, the DSPICSn signals behave as if the CONT bit was not set.
27.7.5 Continuous Serial Communications Clock
The DSPI provides the option of generating a continuous DSPISCK signal for slave peripherals that
require a continuous clock.
Continuous DSPISCK is enabled by setting DMCR[CSCK]. Continuous DSPISCK is only supported for
CPHA = 1. Setting CPHA = 0 will be ignored if the CSCK bit is set. Continuous DSPISCK is supported
for modified transfer format.
Clock and transfer attributes for the continuous DSPISCK mode are set according to the following rules:
• DCTAR0 is used initially. At the start of each SPI frame transfer, the DCTARn specified by the
CTAS for the frame shall be used.
• The currently selected DCTARn remains in use until the start of a frame with a different DCTARn
specified, or the continuous DSPISCK mode is terminated.
It is recommended that the baud rate is the same for all transfers made while using the continuous
DSPISCK. Switching clock polarity between frames while using continuous DSPISCK can cause errors
in the transfer. Continuous DSPISCK operation is not guaranteed if the DSPI is put into the external stop
mode or module disable mode.
Enabling continuous DSPISCK disables the CS to DSPISCK delay and the after DSPISCK delay. The
delay after transfer is fixed at one DSPISCK cycle. Figure 27-21 shows timing diagram for continuous
DSPISCK format with continuous selection disabled.
DSPISCK
(CPOL = 0)
PCSS
t
ASC
DSPISCK
(CPOL = 1)
Master DSPISOUT
t
CSC
t
CSC
t
CSC
= PCSS to DSPISCK delay
t
ASC
= After DSPISCK delay
Master DSPISIN