Freescale Semiconductor MCF5480 - Manual (Page 853)

Initialization and Application Information
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 27-35
27.8.4 Calculation of FIFO Pointer Addresses
The user has complete visibility of the Tx and Rx FIFO contents through the FIFO registers, and valid
entries can be identified through a memory mapped pointer and a memory mapped counter for each FIFO.
The pointer to the first-in entry in each FIFO is memory mapped. For the Tx FIFO the first-in pointer is
the transmit pointer (TXPTR). For the Rx FIFO the first-in pointer is the receive pointer (RXPTR).
Figure 27-23 illustrates the concept of first-in and last-in FIFO entries along with the FIFO counter. The
Tx FIFO is chosen for the illustration, but the concepts carry over to the Rx FIFO. See Section 27.7.2.4,
“Tx FIFO Buffering Mechanism ” and Section 27.7.2.5, “Rx FIFO Buffering Mechanism ” for details on
the FIFO operation.
Table 27-23. Delay Values
Delay Prescaler Values
1 3 5 7
Dela
y Scaler
V
a
lues
2
20.0 ns 60.0 ns 100.0 ns 140.0 ns
4 40.0 ns 120.0 ns 200.0 ns 280.0 ns
8 80.0 ns 240.0 ns 400.0 ns 560.0 ns
16
160.0 ns 480.0 ns 800.0 ns 1.1
µs
32 320.0 ns 960.0 ns 1.6
µs
2.2
µs
64 640.0 ns 1.9
µs
3.2
µs
4.5
µs
128 1.3
µs
3.8
µs
6.4
µs
9.0
µs
256 2.6
µs
7.7
µs
12.8
µs
17.9
µs
512 5.1
µs
15.4
µs
25.6
µs
35.8
µs
1024 10.2
µs
30.7
µs
51.2
µs
71.7
µs
2048
20.5
µs
61.4
µs
102.4
µs
143.4
µs
4096 41.0
µs
122.9
µs
204.8
µs
286.7
µs
8192 81.9
µs
245.8
µs
409.6
µs
573.4
µs
16384
163.8
µs
491.5
µs
819.2
µs
1.1 ms
32768 327.7
µs
983.0
µs
1.6 ms 2.3 ms
65536 655.4
µs
2.0 ms 3.3 ms 4.6 ms