Freescale Semiconductor MCF5480 - Manual (Page 863)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 28-9
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer, and STOP signal. The parts of a communication are described briefly in the following
sections and illustrated in Figure 28-8 .
28.4.1 START Signal
When the bus is free—that is, when no master device is engaging the bus (both SCL and SDA lines are at
logical high)—a master may initiate communication by sending a START signal. A START signal (A in
Figure 28-8 ) is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and awakens all
slaves.
Figure 28-8. Start, Address Transfer, and Stop Signal
28.4.2 Slave Address Transmission
The master sends the slave address in the first byte after the START signal (B in Figure 28-8 ). After the
seven-bit calling address (the slave address), it sends the R/W bit (C), which indicates the slave data
transfer direction (0 = write transfer; 1 = read transfer).
Each slave must have a unique address. An I
2
C master must not transmit its own slave address; it cannot
be master and slave at the same time.
The slave whose address matches that sent by the master pulls SDA low at the ninth serial clock (D) to
return an acknowledge bit.
28.4.3 STOP Signal
The master can terminate the communication by generating a STOP signal (“F” in Figure 28-8 ) to free the
bus. A STOP signal is defined as a low-to-high transition of SDA while SCL is at logical 1. The master
can generate a STOP even if the slave has generated an acknowledge, at which point the slave must release
the bus. The master may also generate a START signal followed by a calling command without generating
a STOP signal first. This is called repeated START. Refer to Section 28.4.6, “Repeated Start .”
28.4.4 Data Transfer
When successful slave addressing is achieved, the data transfer can proceed (E in Figure 28-8 ) on a
byte-by-byte basis in the direction specified by the R/W bit sent by the calling master. Each data byte is 8
bits long.
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0
Slave (or Calling) Address
R/W ACK
Bit
Data Byte
No
ACK
Bit
STOP
Signal
lsb msb lsb msb
SDA
SCL
START
Signal
A
B D
C
E F
SCL held low while
Interrupt is serviced Interrupt bit is set
(Byte complete)
(Master driven) (Master driven)