Freescale Semiconductor MCF5480 - Manual (Page 866)

MCF548x Reference Manual, Rev. 3
28-12 Freescale Semiconductor
Devices with shorter low periods enter a high wait state during this time (see Figure 28-13 ). When all
devices concerned have counted off their low period, the synchronized clock SCL line is released and
pulled high. There is then no difference between the device clocks and the state of the SCL line and all the
devices start counting their high periods. The first device to complete its high period pulls the SCL line
low again.
The relative priority of the contending masters is determined by a data arbitration procedure. A bus master
loses arbitration if it transmits logic "1" while another master transmits logic "0". The losing masters
immediately switch over to slave receive mode and stop driving SDA output (see Figure 28-12 ). In this
case the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware
sets I2SR[IAL] to indicate loss of arbitration.
28.4.8 Handshaking and Clock Stretching
The clock synchronization mechanism can be used as a handshake in data transfers. Slave devices may
hold the SCL low after completion of one byte transfer, which will cause the bus clock to halt, forcing the
master clock into wait status until the slave releases the SCL line.
Figure 28-12. Arbitration Procedure
Slaves may also slow down the bit rate transfer. After the master has driven SCL low, the slave can drive
SCL low for the required period and then release it. If the slave SCL low period is greater than the master
SCL low period, then the resulting SCL bus signal low period is stretched.
Figure 28-13. Clock Synchronization
28.5 Initialization Sequence
Reset will put the I
2
C control register in its default status. Before the interface can be used to transfer serial
data, an initialization procedure must be carried out, as follows:
1. Update I2FDR[IC] to select the required division ratio to obtain the SCL frequency from the
system clock
SCL
SDA by Master1
SDA by Master2
SDA
Master2 Loses Arbitration, and
becomes Slave-Receiver
SCL by Master2
SCL by Master1
SCL
Start Counting High Period
Wait
State