Freescale Semiconductor MCF5480 - Manual (Page 87)

MCF548x External Signals
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 2-17
2.2.1.2 Chip Select (FBCS[5:0])
FBCS[5:0] are asserted to indicate which device is being selected. A particular chip select asserts when
the transfer address is within the device’s address space as defined in the base and mask address registers.
Each chip select can be programmed for a base address location, masking addresses, port size,
burst-capability indication, wait-state generation, and internal/external termination.
Reset clears all chip select programming; FBCS0 is the only chip select initialized out of reset. FBCS0 is
also unique because it can function at reset as a global chip select that allows boot ROM to be selected at
any defined address space. Port size and termination (internal vs. external) for boot FBCS0 are configured
by the levels on AD[2:0] on the rising edge of RSTI, as described in Section 2.2.6, “Reset Configuration
Pins .”
2.2.1.3 Address Latch Enable (ALE)
The assertion of ALE indicates that the MCF548x has begun a bus transaction and that the address and
attributes are valid. ALE is asserted for one bus clock cycle. In multiplexed bus mode, ALE is used
externally as an address latch enable to capture the address phase of the bus transfer.
2.2.1.4 Read/Write (R/W)
The MCF548x drives the R/W signal to indicate the direction of the current bus operation. It is driven high
during read bus cycles and driven low during write bus cycles.
2.2.1.5 Transfer Burst (TBST)
Transfer burst indicates that a burst transfer is in progress. A burst transfer can be 2 to 16 beats depending
on the size of the transfer and the port size.
2.2.1.6 Transfer Size (TSIZ[1:0])
For memory accesses, these signals along with TBST, indicate the data transfer size of the current bus
operation. The FlexBus interface supports byte, word, and longword operand transfers and allows accesses
to 8-, 16-, and 32-bit data ports.
For misaligned transfers, TSIZ[1:0] indicates the size of each transfer. For example, if a longword access
through a 32-bit port device occurs at a misaligned offset of 0x1, a byte is transferred first (TSIZ[1:0] =
01), a word is next transferred at offset 0x2 (TSIZ[1:0] = 10), then the final byte is transferred at offset 0x4
(TSIZ[1:0] = 01).
For aligned transfers larger than the port size, TSIZ[1:0] behaves as follows:
• If bursting is used, TSIZ[1:0] is driven to the size of transfer.
• If bursting is inhibited, TSIZ[1:0] first shows the size of the entire transfer and then shows the port
size.
Table 2-3. Data Transfer Size
TSIZ[1:0] Transfer Size
00 4 bytes (longword)
01 1 byte