Freescale Semiconductor MCF5480 - Manual (Page 876)

MCF548x Reference Manual, Rev. 3
29-2 Freescale Semiconductor
29.1.3 Block Diagram
A block diagram of the complete USB 2.0 Device controller module is shown in Figure 29-1 .
Figure 29-1. USB 2.0 Device Controller Block Diagram
29.1.3.1 Controller and Synchronization
This block handles all of the details of managing the USB protocol and presents a simple set of handshakes
to the application for managing data flow, vendor commands, and configuration information.
The control logic portion of the module implements the control logic and registers that allow the user to
control and communicate with the USB module. The registers are described in Section 29.2.1, “USB
Memory Map .”
The register functions include interrupt status/mask, USB descriptor download, FIFO control and access,
and processing of GET_DESCRIPTOR device requests from control endpoints.
The device core operates on a fixed 30-MHz clock that is generated inside the USB 2.0 physical layer
transceiver (PHY). All other non-core logic runs at the CommBus frequency. The synchronization block
synchronizes the signals that cross between these two clock domains.
29.1.3.2 Descriptor RAM
The descriptor RAM is used to preload the descriptor tables and modify them as necessary. The USB
module can handle the data movement out of this RAM for a USB GET_DESCRIPTOR SETUP
transaction based on the information programmed into the DRAMDR. This operation is described in
Section 29.4.1.1, “USB Descriptor Download ”.
FIFO RAM
FIFO RAM
Manager
FIFO Control
Arbiter
Descriptor
RAM
Integrated USB 2.0 PHY
Comm Bus
USB Controller and Synchronization Logic
Interrupt
USB 2.0 Device Controller