Freescale Semiconductor MCF5480 - Manual (Page 937)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 30-7
30.3.2 Detailed Memory Map (Control/Status Registers)
Table 30-5 shows the FEC register memory map with each register address, name, and a brief description.
Table 30-5. FEC Register Memory Map
MBAR
Offset for
FEC0
MBAR
Offset for
FEC1
Name Byte 0 Byte 1 Byte 2 Byte 3
0x9000 0x9800 Reserved
0x9004 0x9804 Ethernet Interrupt Event Register EIR
0x9008 0x9808 Ethernet Interrupt Mask Register EIMR
0x900C–
0x9020
0x980C–
0x9820
Reserved
0x9024 0x9824 Ethernet Control Register ECR
0x9028–
0x903C
0x9828–
0x983C
Reserved
0x9040 0x9840 MII Data Register MDATA
0x9044 0x9844 MII Speed Control Register MSCR
0x9048–
0x9060
0x9848–
0x9860
Reserved
0x9064 0x9864 MIB Control/Status Register MIBC
0x9068–
0x9080
0x9068–
0x9880
Reserved
0x9084 0x9884 Receive Control Register RCR
0x9088 0x9888 Receive Hash Register RHR
0x908C–
0x90C0
0x988C–
0x98C0
Reserved
0x90C4 0x98C4 Transmit Control Register TCR
0x90C8–
0x90E0
0x98C8–
0x98E0
Reserved
0x90E4 0x98E4 Physical Address Low Register PALR
0x90E8 0x98E8 Physical Address High Register PAHR
0x90EC 0x98EC Opcode / Pause Duration Register OPD
0x90F0–
-0x9114
0x98F0–
-0x9814
Reserved
0x9118 0x9918 Individual Address Upper Register IAUR
0x911C 0x991C Individual Address Lower Register IALR
0x9120 0x9920 Group Address Upper Register GAUR
0x9124 0x9924 Group Address Lower Register GALR