Freescale Semiconductor MCF5480 - Manual (Page 973)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 30-43
30.4 Functional Description
This section describes the operation of the FEC, beginning with the hardware and software initialization
sequence, then the software (Ethernet driver) interface for transmitting and receiving frames.
Following the software initialization and operation sections are sections providing a detailed description
of the functions of the FEC.
30.4.1 Initialization Sequence
This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC,
and what locations the user must initialize prior to enabling the FEC.
30.4.1.1 Hardware Controlled Initialization
In the FEC, registers and control logic are reset by hardware (system reset). A system reset deasserts output
signals and resets general configuration bits.
By clearing ECR[ETHER_EN], the configuration control registers such as the TCR and RCR will not be
reset, but the entire data path will be reset. If ECR[ETHER_EN] is deasserted, the associated FIFO
controller should also be given a soft reset to purge any data/frames.
30.4.1.2 User Initialization (Prior to Asserting ECR[ETHER_EN])
The user needs to initialize portions of the FEC prior to setting the ECR[ETHER_EN] bit. The exact values
will depend on the particular application. The sequence is not important.
FEC registers requiring initialization are defined in
Table 30-44 .
Table 30-43. ECR[ETHER_EN] De-Assertion Effect on FEC
Register/Machine Reset Value
XMIT block Transmission is aborted (bad CRC
appended)
RECV block Receive activity is aborted
Table 30-44. User Initialization (Before Asserting ECR[ETHER_EN])
Description
Initialize EIMR
Clear EIR (write 0xFFFF_FFFF)
Set FECTFWR (optional)
Set IALR / IAUR
Set GAUR / GALR
Set PALR / PAHR (only needed for full duplex flow control)
Set OPD (only needed for full duplex flow control)
Set RCR
Set TCR