Freescale Semiconductor MCF5480 - Manual (Page 977)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 30-47
When the transmit FIFO fills to the watermark (defined by FECTFWR) or a complete (small) frame is
placed in the FIFO, the FEC transmit logic will assert EnTXEN and start transmitting the preamble (PA)
sequence, the start frame delimiter (SFD), and then the frame information from the FIFO. However, the
controller defers the transmission if the network is busy (EnCRS asserts). Before transmitting, the
controller waits for carrier sense to become inactive, then determines if carrier sense stays inactive for 60
bit times. If so, the transmission begins after waiting an additional 36 bit times (96 bit times after carrier
sense originally became inactive). See Section 30.4.12.1, “Transmission Errors ” for more details.
If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller follows
the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached.
When all the frame data has been transmitted, the FCS (frame check sequence) or 32-bit cyclic redundancy
check (CRC) bytes are appended if the TC bit is set in the transmit frame control word (TFCW). If the
ABC bit is set in the TFCW, a bad CRC will be appended to the frame data regardless of the TC bit value.
Following the transmission of the CRC, the Ethernet controller writes the frame status information to the
MIB block. Short frames are automatically padded by the transmit logic (if TFCW[TC] = 1).
Frame (TXF) interrupts may be generated as determined by the settings in the EIMR.
The transmit error interrupts are HBERR, BABT, LC, RL, XFUN, and XFERR. If the transmit frame
length exceeds MAX_FL bytes the BABT interrupt will be asserted, however the entire frame will be
transmitted (no truncation).
To pause transmission, set the GTS (graceful transmit stop) bit in the TCR register. When TCR[GTS] is
set, the FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues
transmission until the current frame either finishes or terminates with a collision. After the transmitter has
stopped, the GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes
transmission with the next frame.
The Ethernet controller transmits bytes least significant bit first.
30.4.5 FEC Frame Reception
The FEC receiver is designed to work with almost no intervention from the host and can perform address
recognition, CRC checking, short frame checking, and maximum frame length checking.
When the driver enables the FEC receiver by setting ECR[ETHER_EN], it will immediately start
processing receive frames. When EnRXDV asserts, the receiver will first check for a valid PA/SFD header.
If the PA/SFD is valid, it will be stripped and the frame will be processed by the receiver. If a valid PA/SFD
is not found, the frame will be ignored.
In 7-wire serial mode, the first 16 bit times of EnRXD0 following assertion of EnRXDV are ignored.
Following the first 16 bit times the data sequence is checked for alternating 1s and 0s. If a 11 or 00 data
sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the
data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is
detected, the PA/SFD sequence is complete.
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur,
but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.
After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame.
Once a collision window (64 bytes) of data has been received and if address recognition has not rejected
the frame, the receive FIFO is signalled that the frame is “accepted.” If the frame is a runt (due to collision)
or is rejected by address recognition, the receive FIFO is notified to “reject” the frame. Thus, no collision
fragments are presented to the user except late collisions, which indicate serious LAN problems.