Freescale Semiconductor StarCore SC140 - Manual (Page 103)

Core Control Registers
SC140 DSP Core Reference Manual 3-3
LF2
Bit 29 Loop Flag 2 — When set, indicates that
hardware loop #3 is enabled. At the start
of an ISR, the SR (including the LF2 bit)
is pushed onto the software stack and
the LF2 bit is cleared.
This bit is cleared at core reset. 0 = Hardware loop #3 not enabled
1 = Hardware loop #3 enabled
LF1
Bit 28 Loop Flag 1 — When set, indicates that
hardware loop #2 is enabled. At the start
of an ISR, the SR (including the LF1 bit)
is pushed onto the software stack and
the LF1 bit is cleared.
This bit is cleared at core reset. 0 = Hardware loop #2 not enabled
1 = Hardware loop #2 enabled
LF0
Bit 27 Loop Flag 0 — When set, indicates that
hardware loop #1 is enabled. At the start
of an ISR, the SR (including the LF0 bit)
is pushed onto the software stack and
the LF0 bit is cleared.
This bit is cleared at core reset. 0 = Hardware loop #1 not enabled
1 = Hardware loop #1 enabled
R
Bits
26–24 Reserved
I2–I0
Bits
23–21 Interrupt Mask Bits — Reflect the
current interrupt priority level (IPL) of the
core. Only non-maskable interrupts or
interrupts with an IPL higher than the
current interrupt mask value can
interrupt the core. The current IPL of the
core can be changed under software
control.
At the start of an ISR, the SR (including
the interrupt mask bits) is pushed onto
the software stack. The interrupt mask
bits are changed to the IPL of the
interrupt being serviced.
The interrupt mask bits are set at core
reset.
For a detailed description of interrupt
service, refer to
Section 5.8, “Exception
Processing,” on page 5-46.
An IPL0 exception is always masked.
Table 3-1. Status Register Description (Continued)
Name Description Settings
I2 I1 I0
Exceptions
Permitted
Exceptions
Masked
0 0 0 IPL 1–7 IPL 0
0 0 1 IPL 2–7 IPL 0–1
0 1 0 IPL 3–7 IPL 0–2
0 1 1 IPL 4–7 IPL 0–3
1 0 0 IPL 5–7 IPL 0–4
1 0 1 IPL 6–7 IPL 0–5
1 1 0 IPL 7 IPL 0–6
1 1 1 NMI IPL 0–7