Freescale Semiconductor StarCore SC140 - Manual (Page 122)

4-12 SC140 DSP Core Reference Manual
Main Capabilities of the EOnCE Module
If the core is in execution state or in a power-saving state (stop or wait) when a debug request is issued, the
core enters debug state. In special cases where the core is frozen (for example, during external access) the
core enters debug state after restart of the core clock.
To exit debug state, set the EX bit in the EOnCE command register (ECR) by the EOnCE command
shifted through the JTAG port. See
Section 4.7.1, “EOnCE Command Register (ECR),” for more details.
Debug state is also exited upon a reset.
4.3.4 Debug Exception
Debug exception is a non-maskable core exception, except for the action of the PICINT bit. The PICINT
bit in the EMCR register acts as a mode/state switch. If PICINT = 1, a debug event that would otherwise
have caused a debug exception asserts instead an EOnCE output to an off-core interrupt controller. If
PICINT = 0, the debug event generates a debug exception. This bit is for the use of the system engineer.
Exception vectors and priorities are described in
Section 5.8, “Exception Processing,” on page 5-46.
Debug exceptions are generated upon the following:
• The event selector (ES) is programmed to generate a debug exception when an appropriate event
occurs.
• The ERCV register is written, and the RCVINT bit in the EMCR register is set.
• The ETRSMT register is read by JTAG, and the TRSINT bit in the EMCR register is set.
• The IME bit in the EMCR register is set, enabling any of the cases that cause the core to enter debug
state.
4.3.5 Executing an Instruction while in Debug State
When the core is in debug state, the host connected to the JTAG port can execute a subgroup of the SC140
instruction set in the core. This is done by eliminating the fetch and dispatch stages from the pipeline, and
performing only decoding and execution of the instruction directly by an AGU execution unit. The host
system writes an instruction to be executed into the core command register (CORE_CMD) together with
the GO command. For more information, see
Section 4.7.1, “EOnCE Command Register (ECR).”
The subgroup of the instructions that can be executed includes:
• All move instructions with all possible addressing modes
• All types of jump and branch instructions with all possible addressing modes (with the exception of
delayed jumps and branches)
• AGU arithmetic instructions
Changes in the state of the core resulting from executing instructions using EOnCE in debug state are the
same as when executing the same instructions using core software.
4.3.6 Software Downloading
The JTAG interface along with the EOnCE can be used to download a program into any core-addressable
memory. To do this, the CHOOSE_EONCE and DEBUG_REQUEST instructions must have already been
executed through the JTAG port, thereby enabling the EOnCE, entering the core into debug state.
Figure 4-7 shows a possible flow for software downloading.