Freescale Semiconductor StarCore SC140 - Manual (Page 157)

EOnCE Controller Registers
SC140 DSP Core Reference Manual 4-47
EE2DEF
Bits 5–4 EE2 Definition — Programs the EE2 signal.
Programmed as an output of the EOnCE, EE2
can indicate detection by EDCA2, working as
a toggle.
Programmed as an input to the EOnCE
according to the programming of the ECNT,
EDU, and ES, EE2 can be programmed to:
• Enable the ECNT together with the
ECNTEN bits
• Enable the EDCA2 together with the
EDCAEN bits
• Generate one of the EOnCE events
together with the ES
EE2 cannot disable EDCA2 or ECNT.
00 = Output, detection by EDCA2
01 = Reserved
10 = Reserved
11 = Input, enables EDCA2 or ECNT, or generates an
EOnCE event
EE1DEF
Bits 3–2 EE1 Definition — Programs the EE1 signal.
Programmed as an output of the EOnCE, EE1
can indicate detection by EDCA1, working as
a toggle. It can also indicate that the core has
entered debug state (debug acknowledge). In
the case of debug acknowledge, when
single-stepping, EE1 does not toggle.
Programmed as an input to the EOnCE
according to the programming of the EDU and
the ES, EE1 can be programmed to enable
EDCA1 or to generate one of the EOnCE
events. 00 = Output, detection by EDCA1
01 = Debug acknowledgement
10 = Reserved
11 = Input, enables EDCA1 or generates an EOnCE
event
EE0DEF
Bits 1–0 EE0 Definition — Programs the EE0 signal.
Programmed as an output of the EOnCE, EE0
can indicate detection by the EDCA0, working
as a toggle.
Programmed as an input to the EOnCE
according to the programming of the EDU and
the ES, the EE0 can be programmed to enable
EDCA0 together with the EDCAEN bits, or
generate one of the EOnCE events together
with the ES.
EE0 can also be programmed to force the core
into debug state. This default state enables
entry into debug state directly after core reset.
Holding EE0 at logic value 1 during and after
the reset enters the core into debug state
before the first dispatch occurs. In this mode,
asserting EE0 also causes an exit from stop or
wait processing states of the core, as specified
in
Section 5.7, “Processing States,” on page
5-41.
When programmed as a debug request, EE0
can also enable EDCA0 or generate an
EOnCE event if EDCA0 or the ES are
programmed in this manner.
00 = Output, detection by EDCA0
01 = Reserved
10 = Input, enables EDCA0 or generates an EOnCE
event
11 = Input, debug request (also enables EDCA0 or
generates an EOnCE event)
Table 4-16. EE_CTRL Description (Continued)
Name Description Settings