Freescale Semiconductor StarCore SC140 - Manual (Page 230)

5-50 SC140 DSP Core Reference Manual
Exception Processing
5.8.3 Maskable Interrupts
5.8.3.1 Interrupt Priority Level
An external maskable interrupt is given a request IPL (between 1 and 7) by driving a 3-bit input along with
the request. The core IPL is held in the I2–I0 bits of the SR. Only interrupts with a request IPL greater than
the core IPL are serviced. Refer to
Section 3.1.1, “Status Register (SR),” on page 3-1, for further
information.
Upon entry to execution, the core priority level is set to be equal to the interrupt priority level of the
serviced interrupt. This prevents interrupts with lower and equal priority level from entering execution.In
particular it prevents the same interrupt, which usually is still asserted, from entering execution again. In
the Interrupt Service Routine the user should typically include an access to the interrupt source to de-assert
the interrupt request, after which the previous interrupt priority level could be lowered, either explicitly or
by executing the RTE instruction which restores the original SR.
5.8.3.2 Controlling All Interrupt Sources
All maskable interrupts can be disabled with the DI instruction, which sets the DI bit in the SR. No
interrupts are serviced after the DI instruction is executed. As a result, the code following the DI
instruction does not need to take into account any possible pipeline effects caused by interrupts.
Non-maskable exceptions are not blocked by the DI instruction. The EI instruction clears the DI bit in the
SR, thus enables all interrupts that are not masked by the IPL bits. The DI and EI instructions do not affect
the IPL bits.
5.8.4 Non-Maskable Interrupts (NMI)
An NMI request is serviced regardless of the current IPL and DI bit values. The only time an NMI request
remains pending is when another NMI is already being serviced. When an NMI service routine enters
execution (namely, the NMI vector is fetched), the NMI disable (NMID) bit in the EMR is set. Refer to
Section 3.1.2, “Exception and Mode Register (EMR),” for a detailed description of the EMR. While this
bit is set, any pending NMI request is not serviced if the core is in normal or exception modes. This bit is
cleared by an RTE or RTED instruction (while the core is in normal or exception mode), or by writing 1 to
it. It cannot be set by the user.
5.8.5 Internal Exceptions
This section describes exceptions generated by conditions inside the core. The internal exceptions (except
the TRAP instruction) are imprecise. These exceptions occur asynchronously after detecting the exception
condition. Thus, they are unable to identify the precise location of the offending instruction. They are used
mostly for diagnostics during program debugging.
In order to aid in the debugging process, a dedicated register in the EOnCE (PC_EXCP) holds the address
of the VLES that caused internal, imprecise exceptions (the Illegal and Overflow exceptions). For multiple
exception types (illegal instruction, illegal execution set, or DALU overflow), the PC_EXCP register will
retrieve the VLES address of the first occurrence of the last exception type. For multiple events of the same
type, only the first event will be sampled in PC_EXCP. For more information on the PC_EXCP register,
see
Section 4.7.8, “PC of the Exception Execution Set (PC_EXCP).”