Freescale Semiconductor StarCore SC140 - Manual (Page 462)

A-148 SC140 DSP Core Reference Manual
DI
DI
Disable Interrupts (AGU)
DI
Description
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
Example 1
di
Instruction Formats and Opcodes
Operation Assembler Syntax
1
→ DI
DI
DI
Sets the DI bit in the status register in order to disable interrupts. The effect is immediate, so the
instructions that execute in the same execution set as well as later execution sets are not interruptible by
maskable interrupts. Non-maskable interrupts and exceptions are not disabled by this bit.
The DI instruction and its counterpart, the EI instruction, can be used to delimit a code segment that needs
to be protected from interruption. For example, a non-interruptible read-modify-write sequence of
execution sets could be written like this:
DI read
modify
EI write
Where read, modify, and write stand for instruction(s). If using this instruction, no allowance is necessary
for a pipeline delay of updating
SR by the DI instruction. This instruction can appear only once in an
execution set.
Register Address Bit Name Description
SR[18] EXP Determines execution working mode.
Register Address Bit Name Description
SR[19] DI Set disable interrupt bit.
Register/Memory Address Before After
SR $0000 0000 $0008 0000
EMR $0000 0000 $0000 0000
Instruction Words Cycles Type Opcode