Freescale Semiconductor StarCore SC140 - Manual (Page 203)

Instruction Timing
SC140 DSP Core Reference Manual 5-23
cycle-by-cycle basis. Accesses issued on the same cycle may cause a contention. The cases where
contentions will occur and how many stall cycles will be introduced depends on the definition of the
memory system, which may be different than that described below.
Example 5-8 provides an execution set that does not cause contention since the instructions execute in
different cycles.
Example 5-8. Parallel Execution of Two Move Instructions
MOVE.L D0,(R0) MOVE.B (R1+1),D1;
;Cycle 1: write to memory
;Cycle 2: read from memory, cycle 2 required by the pre-calculation of (R1+1)
Example 5-9 provides two cases of parallel execution by a bit mask and write instruction. In the example,
it is assumed that the memory accesses are made to addresses that cause contention. In Case A, the read
and write operations scheduled for Cycle 1 will cause contention. In Case B, the two write operations in
Cycle 2 will cause contention.
Example 5-9. Execution Set Containing a Bit Mask and a Move Instruction
A)
BMSET.W #$0008,(R1) MOVE.W D0,($8200);
;Cycle 1: read from (R1); ;write to ($8200)
;Cycle 2: write to (R1)
B)
BMSET.W #$0010,(R1) MOVE.W D1,(R0+2)
;Cycle 1: read from (R1);
;Cycle 2: write to (R1)
;write to (R0+2)
Example 5-10 shows the parallel execution of a bit mask instruction and a move instruction that does not
cause contention. The write operation from the MOVE instruction occurs at Cycle 1. The BMU read
operation occurs at Cycle 2. The BMU write operation that accesses the same location in memory takes
place at Cycle 3.
Example 5-10. Execution Set Containing One Bit Mask Instruction
BMSET.W #$0080,(SP-2) MOVE.W D2,($8200)
;Cycle 1: write to ($8200)
;Cycle 2: read from (SP-2)
;Cycle 3: write to (SP-2)