Instruction formats and opcodes instruction fields, Bmclr #$b646,d7.l – Freescale Semiconductor StarCore SC140 User Manual
Page 390
A-76
SC140 DSP Core Reference Manual
BMCLR
Status and Conditions Changed by Instruction
Example
bmclr #$b646,d7.l
Instruction Formats and Opcodes
Instruction Fields
C1
CCC
Control Registers
DR
HHHH
Data/Address Register
Register Address
Bit Name
Description
Ln
L
Clears the Ln bit in the destination register.
Register/Memory Address
Before
After
immediate
$B646
L7:D7
$0:$0050006C5A
$0:$0050004818
Instruction
Words Cycles Type
Opcode
15
8
7
0
BMCLR #u16,C1.H
2
2
3
0
0
0
1
0
0
0
0
i
i
i
1
0
C C C
1
0
1
i
i
i
i
i
i
i
i
i
i
i
i
i
15
8
7
0
BMCLR #u16,C1.L
2
2
3
0
0
0
1
0
0
0
0
i
i
i
0
0
C C C
1
0
1
i
i
i
i
i
i
i
i
i
i
i
i
i
15
8
7
0
BMCLR #u16,DR.H
2
2
3
0
0
0
0
1
0
0
0
i
i
i
1
H H H H
1
0
1
i
i
i
i
i
i
i
i
i
i
i
i
i
15
8
7
0
BMCLR #u16,DR.L
2
2
3
0
0
0
0
1
0
0
0
i
i
i
0
H H H H
1
0
1
i
i
i
i
i
i
i
i
i
i
i
i
i
000
EMR
010
-
100
—
110
—
001
VBA
011
-
101
SR
111
MCTL
0000
D0
0100
D4
1000
R0
1100
R4
0001
D1
0101
D5
1001
R1
1101
R5
0010
D2
0110
D6
1010
R2
1110
R6
0011
D3
0111
D7
1011
R3
1111
R7
Note:
If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used.