Freescale Semiconductor StarCore SC140 - Manual (Page 751)

Index I-3
CS 4-55
EDCAEN 4-55
EDCAST5-0 (EDCA #5-0 status) 4-42
EDCD (data event detection channel) 4-24
, 4-58
control register (EDCD_CTRL) 4-58
mask register (EDCD_MASK) 4-61
reference value register (EDCD_REF) 4-61
EDCD_CTRL (EDCD control register) 4-58
ATS 4-60
AWS 4-59
CCS 4-60
EDCDEN 4-60
EDCD_MASK (EDCD mark register) 4-61
EDCD_REF (reference value register) 4-61
EDCDEN (EDCD enable) 4-60
EDCDST (EDCD status) 4-42
EDU (event detection unit) 4-54
address event detection channel (EDCA) 4-22 ,
4-54
data event detection channel (EDCD) 4-24 , 4-58
EE pins
control register (EE_CTRL) 4-45
EE_CTRL register
EE0DEF 4-47
EE1DEF 4-47
EE2DEF 4-47
EE3DEF 4-46
EE4DEF 4-46
EE5DEF 4-46
EEDDEF 4-46
EE0DEF (EE0 definition bits) 4-47
EE1DEF (EE1 definition) 4-47
EE2DEF (EE2 definition) 4-47
EE3DEF (EE3 definition) 4-46
EE4DEF (EE4 definition) 4-46
EE5DEF (EE5 definition) 4-46
EEDDEF (EED definition) 4-46
EI A-163
EMCR (EOnCE monitor and control register)
DEBUGERST 4-42
DIS 4-42
EDCAST5-0 4-42
EDCDST 4-42
IME 4-42
RCVINT 4-41
SWDIS 4-42
TBFDM 4-41
TRSINT 4-41
EMR (exception and mode register) 3-7
BEM 3-8
clearing EMR bits 3-10
DOVF 3-8
GP6-0 3-8
ILIN 3-9
ILST 3-9
NMID 3-8
Emulation and debug 4-1
Endian support 2-56
bit mask instructions 2-67
change-of-flow instructions 2-68
control instructions 2-68
data moves 2-58
data transfer 2-59
instruction word transfers 2-62
memory access behavior 2-64
multi-register transfer 2-61
stack support instructions 2-67
EOnCE 1-3
EOnCE (enhanced on-chip emulator) 1-3
, 2-5 , 4-1 ,
4-10
command registers (ECR) 4-36
dedicated instructions 4-11
EE pins 4-18
internal architecture 4-16
register addressing 4-30
register addressing offsets 4-31
EOnCE controller
functionality 4-15
register set 4-17
EOnCE controller registers
command register (ECR) 4-36
core command register (CORE_CMD) 4-48
monitor and control register (EMCR) 4-41
PC breakpoint detection register
(PC_DETECT) 4-49
PC of last execution set (PC_LAST) 4-49
PC of the exception execution set (PC_EXCP) 4-49
PC of the next execution set (PC_NEXT) 4-49
receive register (ERCV) 4-43
status register (ESR) 4-37
transmit register (ETRSMT) 4-43
EOnCE pins 4-10
EOR A-165
, A-167
EOR.W A-169
ES (event selector) 4-25
, 4-61
control register (ESEL_CTRL) 4-61
mask debug exception register (ESEL_DI) 4-64
mask debug mode register (ESEL_DM) 4-63
mask disable trace register (ESEL_DTB) 4-65
mask enable trace register (ESEL_ETB) 4-64
ESEL_CTRL (ES control register) 4-26
SELDI 4-62
SELDM 4-62
SELDTB 4-62
SELETB 4-62
ESEL_DI (ES mask debug exception register) 4-26 ,
4-64
ESEL_DM (ES mask debug mode register) 4-26 , 4-63