Freescale Semiconductor StarCore SC140 - Manual (Page 89)

Memory Interface
SC140 DSP Core Reference Manual 2-57
The two data buses that connect between the core and the memory are each 64 bits wide. Instructions such
as load to registers and store to memory utilize the bus according to the application requirement. Different
versions of the instructions are used for different bandwidths such that:
• MOVE.B loads or stores bytes (8 bits).
• MOVE.W and MOVE.F load or store integer or fractional words (16 bits).
• MOVE.2W, MOVE.2F, and MOVE.L load or store double-integers, double-fractions, and long
words respectively (32 bits).
• MOVE.4W, MOVE.4F, and MOVE.2L load or store quad-integers, quad-fractions, and double-long
words respectively (64 bits).
Figure 2-20 shows the data busses between the SC140 core and the memory.
Figure 2-20. Basic Connection between SC140 Core and Memory
2.4.1.2 Memory Organization
Different types of data are stored differently in memory for each of the two endian modes. However, the
data retains the same meaning. For example, 64 bits of data can be represented by any of the following:
• Eight 8-bit bytes
• Four 16-bit numbers
• Two 32-bit numbers
Figure 2-21 shows how data is organized in memory in the two endian modes. Each data unit is a byte
made of two hexadecimal numbers.
Figure 2-21. Memory Organization of Big and Little Endian Mode
Unified
Memory
Space
SC140 Core
128-bit PDB-bus
64-bit XDBA-bus
64-bit XDBB-bus
0
8
16 ($10)
7 6 5 4 3 2 1 0
Little Endian
8
16 ($10)
0 1 2 3 4 5 6 7
Big Endian
0 0a 0b 0c 0d 0e 0f 0f 0e 0d 0c 0b 0a
01 02 03 04 05 06 07 08 07 08 05 06 03 04 01 02
11 22 33 44 cc dd ee ff cc dd ee ff 11 22 33 44