Freescale Semiconductor StarCore SC140 - Manual (Page 121)

Main Capabilities of the EOnCE Module
SC140 DSP Core Reference Manual 4-11
4.3.2 EOnCE Dedicated Instructions
The instruction set of the SC140 core architecture includes three instructions which are dedicated to the
EOnCE module and available for debugging purposes:
• DEBUG — Upon decoding by the core, if the SDD bit in EMR is clear, the core enters the debug
processing state.
• DEBUGEV — This instruction indicates to the EOnCE that a debug event has occurred. The
EOnCE handles the instruction according the settings of the event selector control registers.
• MARK — Upon execution by the core when the TMARK bit in the TB_CTRL register is set, its
program counter (PC) value is put into the trace buffer. This enables it to mark the different parts of
application code that can be executed by different threads. See
Section 4.11.1, “Trace Buffer Control
Register (TB_CTRL),” for further details.
4.3.3 Debug State
Debug state is a special core processing state in which the pipeline is stalled, waiting for commands from
the EOnCE through the JTAG port. All the execution units are ready to operate, but the PSEQ dispatcher
module does not dispatch any new execution sets to the execution units. Peripherals can include control
bits that determine whether they continue to operate in debug state.
Two actions are possible in debug state:
• Execute a Single Step — The core leaves debug state for one cycle. The currently fetched
execution set is executed, after which the core then returns to debug state and the PSEQ proceeds to
the next execution set.
• Insert an Instruction from the JTAG port or EOnCE — A MOVE, JMP, or BRA instruction can be
inserted and executed without the core leaving debug state.
The core can be put into debug state by a request from the EOnCE when:
• The DEBUG instruction is issued.
• The EE0 signal is asserted at the exit from reset.
• The EE0 signal is asserted when configured as a debug request (default behavior).
• The JTAG DEBUG_REQUEST instruction is issued at any time, including when the core is exiting
reset.
• Assertion a debug request input, to be used for system requests. The usage of this input is SoC
specific.
• The trace buffer is full and the TBFDM bit is set in the EOnCE monitor and control register
(EMCR).
• The event selector (ES) is programmed to enter the core into debug state upon the detection of an
appropriate event.
When the EE0 signal causes the core to enter debug state, the signal must be asserted until the user receives
debug acknowledgement.
Asserting the EE0 pin or the JTAG DEBUG_REQUEST instruction signal during reset until getting debug
acknowledge will place the core into debug processing state before the first VLES fetch.