Freescale Semiconductor StarCore SC140 - Manual (Page 246)

6-66 SC140 DSP Core Reference Manual
Core Assembly Syntax with an ISAP
This is similar example to that shown in Section 6.7.1, “Identification of ISAP instructions,” but instead of
the ISAP tsteq instruction, a special move from a memory location to ISAP register k0 is used. The
special ISAP move instruction (called permute_lsb_set.2l in this case) can read 64-bit data, permute
the bytes according to a certain definition, set the LSB, and write the result to register k0.
In this case, the ISAP assembler translates its move instruction to a core move instruction with dummy
core registers d0,d1 - move.2l (r0)+,d0:d1. This example is aimed to show how complex some
specialized ISAP instructions may get, and why it is not desirable to constrain their syntax.
6.7.3 Conditional Execution
ISAP instructions can be conditionally executed by using the core IFc prefix instruction. By definition, the
IFc mnemonics imply prefix predication. A VLES can have up to two IFc groups.
The following syntax conventions and limitations apply to conditionally executing ISAP instructions (See
also Rule G.P.9):
• IFc mnemonic must be outside any ISAP clause (predication is the property of the core syntax, even
if predicating only an ISAP clause as in the case of the iff in the above example)
• There can be two ISAP clauses per VLES, each belonging to a different IFc group.
• ISAP ALU instructions must all be in the same IFc group
• Implicit Core AGU instructions generated to support ISAP move instructions are subject to the same
limitations as other core AGU instructions. This means for example:
— If the VLES includes two IFc groups, and there are two ISAP move instructions, then the each
ISAP move must be in a different IFc group.
The IFc predication convention is supported by ISAP interface signals that inform the ISAP of the
predication status for each AGU instruction (associated with a data bus).
According to Rule G.P.9, it is not allowed to have two ISAP ALU instructions in two IFc groups.
However, ISAP move instructions will cause the assembler to generate implicit core MOVE instruction,
which could be in different IFc groups. For more details on how this works, see
Section 6.4, “ISAP
Memory Access,” on page 6-60.
Example 6-6. Conditional Execution Example
ift inc d0 {move.w (r0),k0} iff {tfra k0,k1 move.l (r1),k5}
The move instructions inside the ISAP brackets translates into an implicit core MOVE instructions, each
conditioned by a different IFc condition.
Example 6-7. Conditional Execution Example
1 [ ift mac d0,d2,d4 mac d1,d3,d5
2 iff {alu_instruction k0,k1,k2
3 move_special.w k2,(r1)+}
4 move.l (r0)+,r2]