Description – Freescale Semiconductor StarCore SC140 User Manual
Page 737
VSL
SC140 DSP Core Reference Manual
A-423
Description
The VSL instructions are intended to optimize the implementation of the Viterbi decoder algorithm. They
are used in conjunction with the MAX2VIT instruction, which sets the Viterbi flags and stores the
maximum portions of data register pairs into the destination registers for use with VSL. See MAX2VIT,
page A-249.
The VSL instructions do not behave the same in little and big endian modes, meaning that data in source
registers is written to different memory locations in the two modes. This behavior requires that the
software implementation of Viterbi algorithms be different for the two endian modes. See
on page 2-56, for more detail on bus and memory behavior for each mode.
Note:
The values in the data registers are not changed by these instructions.
VSL.4W D2:D6:D1:D3,(Rn)+N0
Writes four consecutive words taken from the LP of the source data registers to the memory. D2.L and
D6.L are written to the location of the first two words in the memory, the order of which depends on the
endian mode. The next two words written are: 1) A left-shifted value of D1.L or D3.L, according to the
Viterbi flag VF0. If the Viterbi flag VF0 is set, then the left-shifted D3.L is chosen. Otherwise, the
left-shifted D1.L is chosen and the LSB is filled with zero. 2) A left-shifted value of D1.L or D3.L,
according to the Viterbi flag VF2. If the Viterbi flag VF2 is set, then the left-shifted D3.L is chosen.
Otherwise, the left-shifted D1.L is chosen and the LSB is filled with one. The order of these two words
depends on the endian mode. The address register values used with this instruction must be quad
word-aligned (a multiple of 8).
VSL.4F D2:D6:D1:D3,(Rn)+N0
Writes four consecutive words taken from the HP of the source data registers to the memory. D2.H and
D6.H are written to the location of the first two words in the memory, the order of which depends on the
endian mode. The next two words that are written are: 1) A left-shifted value of D1.H or D3.H, according
to the Viterbi flag VF1. If the Viterbi flag VF1 is set, then the left-shifted D3.H is chosen. Otherwise, the
left-shifted D1.H is chosen and the LSB is filled with zero. 2) A left-shifted value of D1.H or D3.H,
according to the Viterbi flag VF3. If the Viterbi flag VF3 is set, then the left-shifted D3.H is chosen.
Otherwise, the left-shifted D1.H is chosen and the LSB is filled with one. The address register values used
with this instruction must be quad word-aligned (a multiple of 8).
VSL.2W D1:D3,(Rn)+N0
Writes two consecutive words taken from the LP of the source data registers to the memory, the order of
which depends on the endian mode. These words are: 1) A left-shifted value of D1.L or D3.L, according to
the Viterbi flag VF0. If the Viterbi flag VF0 is set, then the left-shifted D3.L is chosen. Otherwise, the
left-shifted D1.L is chosen and the LSB is filled with zero. 2) A left-shifted value of D1.L or D3.L,
according to the Viterbi flag VF2. If the Viterbi flag VF2 is set, then the left-shifted D3.L is chosen.
Otherwise, the left-shifted D1.L is chosen and the LSB is filled with one. The address register values used
with this instruction must be long word-aligned (a multiple of 4).
VSL.2F D1:D3,(Rn)+N0
Writes two consecutive words taken from the HP of the source data registers to the memory, the order of
which depends on the endian mode. These words are: 1) A left-shifted value of D1.H or D3.H, according to
the Viterbi flag VF1. If the Viterbi flag VF1 is set, then the left-shifted D3.H is chosen. Otherwise, the
left-shifted D1.H is chosen and the LSB is filled with zero. 2) A left-shifted value of D1.H or D3.H,
according to the Viterbi flag VF3. If the Viterbi flag VF3 is set, then the left-shifted D3.H is chosen.
Otherwise, the left-shifted D1.H is chosen and the LSB is filled with one. The address register values used
with this instruction must be long word-aligned (a multiple of 4).