Chapter2 core architecture, 1 architecture overview, Chapter 2 – Freescale Semiconductor StarCore SC140 User Manual
Page 33: Architecture overview -1, Chapter 2, “core architecture, Chapter 2 core architecture
SC140 DSP Core Reference Manual
2-1
Chapter 2
Core Architecture
This chapter provides an overview of the SC140 core architecture. It describes the main functional blocks
and data paths of the core.
2.1 Architecture Overview
The SC140 core provides the following main functional units:
•
Data arithmetic and logic unit (DALU)
•
Address generation unit (AGU)
•
Program sequencer unit (PSEQ)
To provide data exchange between the core and the other on-chip blocks, the following buses are
implemented:
•
Two data memory buses (address and data pairs: XABA and XDBA, XABB and XDBB) that are
used for all data transfers between the core and memory.
•
Program data and address buses (PDB and PAB) for carrying program words from the memory to
the core.
•
Special buses to support tightly coupled external user-definable instruction set accelerators.
A block diagram of the SC140 core is shown in Figure 2-3.