Freescale Semiconductor StarCore SC140 - Manual (Page 132)

4-22 SC140 DSP Core Reference Manual
EOnCE Module Internal Architecture
4.5.3.1 Address Event Detection Channel (EDCA)
One of the main elements of the EDU is the EDCA. An EDCA has all the logic required to detect address
values according to a user-programmable configuration.
There is no support for breakpoints on the PC of an instruction that is not the first instruction of the
execution set. All PC detections are done at execution set level.
Figure 4-11 shows the EDCA block diagram.
Figure 4-11. EDCA Block Diagram
Two 32-bit comparators are used to compare the core address buses and the reference values programmed
into the reference value registers EDCAi _REFA and EDCAi _REFB. Each comparator is capable of
detecting one of the following four conditions:
• Equal
• Not equal
• Less than
XA
BA
XABB
Memory Bus and
Reference Value Register A
Comparator A
Event
Selection
Eventi
Control Register
Access Type Select
Reference Value Register B
Comparator B
>=< >=<
MUX
Event[i+2 mod 6]
Event[i+4 mod 6]
Count Event
PC
MASK Register
Event[i+1 mod 6]
Event[i+3 mod 6]
Event[i+5 mod 6]
EEi
EventD
External Event 6
External Event 7