Freescale Semiconductor StarCore SC140 - Manual (Page 708)

A-394 SC140 DSP Core Reference Manual
SUBA
SUBA
Subtract (AGU)
SUBA
Description
This instruction subtracts an immediate or an AGU register from another AGU register. For R0-R7
destinations, this instruction is affected by the modifier mode selected in MCTL.
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
None.
Example
suba r1,r0
Operation Assembler Syntax
Rx – #u5
→ Rx
SUBA #u5,Rx {0
≤ u5 < 64}
Rx – rx
→ Rx
SUBA rx,Rx
SUBA #u5,Rx
Subtracts an immediate unsigned 5-bit integer from an AGU register (Rx) and stores the result in the same
register. If the stack pointer is the destination operand, then the immediate value must be a multiple of eight
since the resulting 3 LSBs are forced to zero.
SUBA rx,Rx
Subtracts one AGU register (rx) from another (Rx) and stores the result in the destination AGU register
(Rx). If the stack pointer is the destination operand, then the value in rx must be a multiple of eight since
the resulting 3 LSBs are forced to zero.
Register Address Bit Name Description
SR[18] EXP Determines which stack pointer is used when the stack pointer is an
operand. Otherwise, the instruction is not affected by SR.
MCTL[31:0] AM3–AM0 Address modification bits when updating R0–R7. Otherwise, the
instruction is not affected by MCTL.
Register/Memory Address Before After
MCTL $0000 0000
R1 $0000 0001
R0 $0000 0010 $0000 000F