Freescale Semiconductor StarCore SC140 User Manual
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SC140 DSP Core Reference Manual
EOnCE Controller Registers
DEBUGERST
Bits 21–18
Debugger Status Information — If several applications (debugger processes) try
to connect to the core, unaware of each other, DEBUGERST bits serve as flags.
Reset once the core is powered, they can be set/reset by the application as an
occupy signal. The debugger may use these bits to reserve the core for its use.
In case the host disconnects from the core or goes down, when the host
(debugger) tries to regain control on the core, it can use the DEBUGERST bits to
find out at when the host disconnected. This is extremely useful when the host is
connected to the core through a network rather than direct cables.
SWDIS
Bit 17
Software Access Disable — Enables the debug host to lock the EOnCE. When
the bit is set, software write access is denied to all the EOnCE registers except the
ETRSMT register. Software read access is denied from the trace buffer.
IME
Bit 16
Interrupt Mode Enable — When set, this bit causes the core to execute a debug
exception instead of entering debug state for any of the source events that would
have put the core in debug state. This bit can only be changed when all debug
request sources are disabled, specifically when there are no debug requests from
the external source (JTAG port, EE pin or system debug request), trace buffer,
event selector or from the execution of a debug instruction.
Debug request signals from external sources should not normally be used as a
source for debug exceptions. If they are used, the interrupt request should be kept
asserted until the core acknowledges it to the driver by some agreed SW protocol.
The core then must acknowledge that the interrupt was de-asserted before the
driver may assert it again.
DIS
Bit 15
Debug Interrupt Status — Sticky bit that is set by the EOnCE when a debug
exception is generated. When a user resets this bit, all the debug reason bits of the
ESR are reset.
R
Bits 14–9
Reserved
EDCDST
Bit 8
EDCD Status — Sticky bit that is set by the EOnCE upon event detection by the
EDCD. Should be cleared by the user.
EDCAST7
Bit 7
EDCA7 Status — Sticky bit that is set by the EOnCE upon event detection by the
optional external EDCA7. It should be cleared by the user.
EDCAST6
Bit 6
EDCA6 Status — Sticky bit that is set by the EOnCE upon event detection by the
optional external EDCA6. It should be cleared by the user.
EDCAST5
Bit 5
EDCA5 Status — Sticky bit that is set by the EOnCE upon event detection by
EDCA5. It should be cleared by the user.
EDCAST4
Bit 4
EDCA4 Status — Sticky bit that is set by the EOnCE upon event detection by
EDCA4. It should be cleared by the user.
EDCAST3
Bit 3
EDCA3 Status — Sticky bit that is set by the EOnCE upon event detection by
EDCA3. It should be cleared by the user.
EDCAST2
Bit 2
EDCA2 Status — Sticky bit that is set by the EOnCE upon event detection by
EDCA2. It should be cleared by the user.
EDCAST1
Bit 1
EDCA1 Status — Sticky bit that is set by the EOnCE upon event detection by
EDCA1. It should be cleared by the user.
EDCAST0
Bit 0
EDCA0 Status — Sticky bit that is set by the EOnCE upon event detection by
EDCA0. It should be cleared by the user.
Table 4-15. EMCR Description (Continued)
Name
Description