Freescale Semiconductor StarCore SC140 - Manual (Page 47)

DALU
SC140 DSP Core Reference Manual 2-15
The Ln bit is calculated (and set or cleared) for the following saturable instructions: ABS, ADC, ADR,
ADD, ADDNC, ASL, ASR, DIV, INC, MAC, MACR, MPY, MPYR, NEG, RND, SBC, SBR, SUB,
SUBL, SUBNC, and TFRx. The Ln bit is cleared if arithmetic saturation mode is set, except for these
instructions: ADC, DIV, SBC, TFR, TFRT, and TFTF. For the latter six, the Ln bit calculation is done,
even if arithmetic saturation mode is set. However, no scaling is considered in the Ln bit calculation if the
arithmetic saturation mode is set, even if a scaling mode bit is set.
The Ln bit is always cleared as a result of the execution of one of the following instructions: CLR,
DECEQ, DECGE, MAX, MAXM, MIN, ADD2, SUB2, MAX2, MAX2VIT, DMACsu, DMACss,
MACsu, MACuu, MACus, MPYsu, MPYuu, MPYus, IADDNC, SAT, all integer multiplication
operations, all BFU operations (as listed in Table 2-6 on page 2-13), and all MOVE instructions except for
the specialized MOVE instruction that restores (pops the stack) the extension and Ln bits from memory. If
the result of these instructions is required to be limited by a following move operation (a TFR Dn), the Dn
instruction should be executed after the original instruction in order to validate the Ln bit before the value
is written to memory using a MOVES.x operation.
2.2.1.6.2 Limiting with the MOVES Instructions
The second stage of limiting occurs with the execution of a MOVES instruction. A limited value is
substituted for the transferred data if the Ln bit of that register was set. The data in the register is not
changed, only the data transferred.
Having four limiters for each bus allows eight operands to be limited independently in the same instruction
cycle. The four data limiters per bus can also be combined to form two 32-bit data limiters per bus for
long-word operands.
If limiting occurs, the data limiter substitutes a limited data value having maximum magnitude (saturated)
and the same sign as the 40-bit source register content:
• $7FFF for 16-bit positive numbers
• $7FFF FFFF for 32-bit positive numbers
• $8000 for 16-bit negative numbers
• $8000 0000 for 32-bit negative numbers
This substitution process is sometimes called transfer saturation. The value in the register is not shifted or
limited, and can be reused by subsequent instructions. If the arithmetic saturation mode is set in the SR,
scaling is not considered in the calculation of the Ln bit. An example of limiting is provided in Table 2-9.
Table 2-8. Ln Bit Calculation
S1 S0 Scaling Mode Bits Defining the Ln bit Calculation
0 0 No Scaling Bits 39, 38..............32, 31
0 1 Scale Down Bits 39, 38..............33, 32
1 0 Scale Up Bits 39, 38..............31, 30