Macr, Signed fractional multiply-accumulate, Operation assembler syntax – Freescale Semiconductor StarCore SC140 User Manual
Page 550
A-236
SC140 DSP Core Reference Manual
MACR
MACR
Signed Fractional Multiply-Accumulate
MACR
and Round (DALU)
Description
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
Example
macr d4,d5,d6
Operation
Assembler Syntax
Rnd(Dn
± (Da.H * Db.H)) → Dn
MACR
±Da,Db,Dn
MACR
±Da,Db,Dn
This instruction performs signed fractional multiplication of two 16-bit signed operands (Da.H and Db.H).
It then adds or subtracts the product to or from a destination data register (Dn) and rounds the final result.
Rounding adjusts the LSB of the high part of the destination register according to the value of the low part
of the register, and then zeros the low part. The two modes of the round function Rnd (), are described on
page A-359.
Register Address
Bit Name
Description
SR[2]
SM
If set, selects 32-bit arithmetic saturation mode.
SR[3]
RM
Rounding mode
SR[5:4]
S[1:0]
The scaling mode bits determine which bits in the result are used in
the Ln bit calculation and which bits are used in rounding.
Register Address
Bit Name
Description
Ln
L
If not in arithmetic saturation mode (SR [SM] = 0), calculates and
updates the Ln bit in the destination register. If in arithmetic
saturation mode (SR [SM] = 1), clears the Ln bit in the destination
register.
EMR[2]
DOVF
Set if the result cannot be represented in 40 bits, or if the result
saturates to 32 bits in arithmetic saturation mode.
Register/Memory Address
Before
After
SR
$00E0 0000
D4
$00 0080 0000
D5
$00 0080 0000
L6:D6
$0:$00 0007 0000
$0:$00 0008 0000